llvm-svn: 118736

llvm-svn: 118732

llvm-svn: 118730

llvm-svn: 118720

double quoting of ObjC symbol names in constant pool entries.

rdar://8652107

llvm-svn: 118688

VariantKind marker to indicate the additional information necessary. Update
MC to handle the new Kinds. rdar://8647623

llvm-svn: 118671

llvm-svn: 118662

llvm-svn: 118656

llvm-svn: 118653

llvm-svn: 118648

llvm-svn: 118644

as derived from the target triple.  This is important for enabling
features that are implied based on the architecture version.

llvm-svn: 118643

It is only supported for ARM code.  Normally Thumb2 code would use DMB instead,
but depending on how the compiler is invoked (e.g., -mattr=-db) that might be
disabled.  This prevents a "cannot select MEMBARRIER_MCR" error in that
situation.  Radar 8644195

llvm-svn: 118642

* LDM, et al, uses a bit mask to indicate the register list.
* VLDM, et al, uses a base register plus number.

The LDM instructions may be non-contiguous, but the VLDM ones must be
contiguous. Those are semantic checks that should be done later in the
compiler. Also postpone the creation of the bit mask until it's needed.

llvm-svn: 118640

help in MC'izing the references that use them.

llvm-svn: 118633

pseudo-label. (TLS stuff).

llvm-svn: 118609

llvm-svn: 118606

object file emission.

llvm-svn: 118601

llvm-svn: 118600

a left shift by zero.

llvm-svn: 118587

llvm-svn: 118586

llvm-svn: 118513

constant pool references and global variable refernces to resolve properly
for object file generation. For example,

int x;
void foo(unsigned a, unsigned *p) {
  p[a] = x;
}

can now be successfully compiled directly to an (ARM mode) object file.

llvm-svn: 118469

llvm-svn: 118462

llvm-svn: 118458

llvm-svn: 118457

number of registers in the list.

llvm-svn: 118456

llvm-svn: 118453

llvm-svn: 118446

llvm-svn: 118429

llvm-svn: 118422

llvm-svn: 118413

an initial implementation and may change once reglists are fully fleshed out.

llvm-svn: 118390

llvm-svn: 118389

llvm-svn: 118375

the registers, because the register numbers may be much greater than the number
of bits available in the machine's register.

I extracted the register list verification code out of the actual parsing of the
registers. This made checking for errors much easier. It also limits the number
of warnings that would be emitted for cascading infractions.

llvm-svn: 118363

to satisfy the ClassifyOperand method of the Asm matcher without having to add a
RegList type to every back-end.

llvm-svn: 118360

- Make ARMOperand a class so that some things are internal to the class.
- Reformatting.

llvm-svn: 118357

(surprise!) a list of registers. Register lists are consecutive, so we only need
to record the start register plus the number of registers.

llvm-svn: 118351

llvm-svn: 118341