llvm-svn: 111019

llvm-svn: 111001

llvm-svn: 111000

numbers match. The old check could accidentally leave holes in openli.

Also let useIntv add all ranges for the phi-def value inserted by
enterIntvAtEnd. This works as long at the value mapping is established in
enterIntvAtEnd.

llvm-svn: 110995

function to do it.

llvm-svn: 110994

llvm-svn: 110987

Move some code from Verifier into SVI::isValidOperands.  This allows us to catch bad shufflevector operations when they are created, rather than waiting for someone to notice later on.

llvm-svn: 110986

llvm-svn: 110983

llvm-svn: 110982

llvm-svn: 110981

This can happen if the original interval has been broken into two disconnected
parts. Ideally, we should be able to detect when the graph is disconnected and
create separate intervals, but that code is not implemented yet.

Example:

Two basic blocks are both branching to a loop header. Our interval is defined in
both basic blocks, and live into the loop along both edges.

We decide to split the interval around the loop. The interval is split into an
inside part and an outside part. The outside part now has two disconnected
segments, one in each basic block.

If we later decide to split the outside interval into single blocks, we get one
interval per basic block and an empty dupli for the remainder.

llvm-svn: 110976

split intervals. THis means the analysis can be used for multiple splits as long
as curli doesn't shrink.

llvm-svn: 110975

before it rewrites the code, we need to use that in the post-rewrite pass.

llvm-svn: 110962

llvm-svn: 110954

the memory barrier variants (other than 'SY' full system domain read and write)
are treated as one instruction with option operand.

llvm-svn: 110951

If a phi-def value were removed from the interval, the phi-kill flags are no
longer valid.

llvm-svn: 110949

Make sure ARM constant island pass does not break up an IT block. If the split point is in the middle of an IT block, it should move it up to just above the IT instruction. rdar://8302637

llvm-svn: 110947

- Teach SSEDomainFix to switch between different levels of AVX instructions. Here we guess that AVX will have domain issues, so just implement them for consistency  and in the future we remove if it's unnecessary.
- Make foldMemoryOperandImpl aware of 256-bit zero vectors folding and support the 128-bit counterparts of AVX too.
- Make sure MOV[AU]PS instructions are only selected when SSE1 is enabled, and duplicate the patterns to match AVX.
- Add a testcase for a simple 128-bit zero vector creation.

llvm-svn: 110946

llvm-svn: 110944

llvm-svn: 110940

llvm-svn: 110937

Before spilling a live range, we split it into a separate range for each basic
block where it is used. That way we only get one reload per basic block if the
new smaller ranges can allocate to a register.

This type of splitting is already present in the standard spiller.

llvm-svn: 110934

having it finish processing all of the muliply operands before
starting the whole getAddExpr process over again, instead of
immediately after the first simplification.

llvm-svn: 110916

llvm-svn: 110915

by having it finish processing the whole operand list before
starting the whole getAddExpr process over again, instead of
immediately after the first duplicate is found.

llvm-svn: 110914

target triple and straightens it out.  This does less than gcc's script
config.sub, for example it turns i386-mingw32 into i386--mingw32 not
i386-pc-mingw32, but it does a decent job of turning funky triples into
something that the rest of the Triple class can understand.  The plan
is to use this to canonicalize triple's when they are first provided
by users, and have the rest of LLVM only deal with canonical triples.
Once this is done the special case workarounds in the Triple constructor
can be removed, making the class more regular and easier to use.  The
comments and unittests for the Triple class are already adjusted in this
patch appropriately for this brave new world of increased uniformity.

llvm-svn: 110909

in an external testsuite.

llvm-svn: 110905

llvm-svn: 110898

term goal here is to be able to match enough of vector_shuffle and build_vector
so all avx intrinsics which aren't mapped to their own built-ins but to
shufflevector calls can be codegen'd. This is the first (baby) step, support
building zeroed vectors.

llvm-svn: 110897

entry for ARM STRBT is actually a super-instruction for A8.6.199 STRBT A1 & A2.
Recover by looking for ARM:USAT encoding pattern before delegating to the auto-
gened decoder.

Added a "usat" test case to arm-tests.txt.

llvm-svn: 110894

because it could have an ambiguous suffix.

llvm-svn: 110890

instructions onto the target specific parser, which can do a better job.

llvm-svn: 110889

target specific parsers can adapt the TargetAsmParser to this.

llvm-svn: 110888

Added two test cases to arm-tests.txt.

llvm-svn: 110880

Tested by scope.exp in gdb testsuite.

llvm-svn: 110876

instruction opcode.  This also fixes part of PR7792.

llvm-svn: 110875

When a register is defined by a partial load:

  %reg1234:sub_32 = MOV32mr <fi#-1>; GR64:%reg1234

That load cannot be folded into an instruction using the full 64-bit register.
It would become a 64-bit load.

This is related to the recent change to have isLoadFromStackSlot return false on
a sub-register load.

llvm-svn: 110874

llvm-svn: 110863

 - remove ashr which never worked.
 - fix lshr and shl and add tests.
 - remove dead function "intersect1Wrapped".
 - add a new sub method to subtract ranges, with test.

llvm-svn: 110861

and remove casts from all its callers.

llvm-svn: 110848