- Sep 25, 2013
-
-
Eli Friedman authored
PR17338. llvm-svn: 191337
-
- Sep 24, 2013
-
-
Andrew Trick authored
llvm-svn: 191312
-
Benjamin Kramer authored
No functionality change, lots of indentation changes. llvm-svn: 191303
-
Jiangning Liu authored
Patch by Ana Pazos. 1.Added support for v1ix and v1fx types. 2.Added Scalar Pairwise Reduce instructions. 3.Added initial implementation of Scalar Arithmetic instructions. llvm-svn: 191263
-
Michael Gottesman authored
Sometimes a copy from a vreg -> vreg sneaks into the middle of a terminator sequence. It is safe to slice this into the stack protector success bb. This fixes PR16979. llvm-svn: 191260
-
Eric Christopher authored
llvm-svn: 191257
-
Eric Christopher authored
checking patch until we get full dumping support. llvm-svn: 191239
-
Eric Christopher authored
llvm-svn: 191236
-
Eric Christopher authored
llvm-svn: 191235
-
- Sep 23, 2013
-
-
Bill Wendling authored
llvm-svn: 191226
-
Eric Christopher authored
a) Make sure we are emitting the correct section in our section labels when we begin the module. b) Make sure we are emitting the correct pubtypes section in the presence of gnu pubtypes. c) For C++ struct, union, class, and enumeration types are default external. llvm-svn: 191225
-
Kay Tiong Khoo authored
llvm-svn: 191214
-
Richard Mitton authored
The size of common symbols is now tracked correctly, so they can be listed in the arange section without needing knowledge of other following symbols. .comm (and .lcomm) do not indicate to the system assembler any particular section to use, so we have to treat them as having no section. Test case update to account for this. llvm-svn: 191210
-
- Sep 22, 2013
-
-
Benjamin Kramer authored
This makes using array_pod_sort significantly safer. The implementation relies on function pointer casting but that should be safe as we're dealing with void* here. llvm-svn: 191175
-
Tim Northover authored
Previously, the DAGISel function WalkChainUsers was spotting that it had entered already-selected territory by whether a node was a MachineNode (amongst other things). Since it's fairly common practice to insert MachineNodes during ISelLowering, this was not the correct check. Looking around, it seems that other nodes get their NodeId set to -1 upon selection, so this makes sure the same thing happens to all MachineNodes and uses that characteristic to determine whether we should stop looking for a loop during selection. This should fix PR15840. llvm-svn: 191165
-
- Sep 21, 2013
-
-
Juergen Ributzka authored
This reverts commit r191130. llvm-svn: 191138
-
Juergen Ributzka authored
The Type Legalizer recognizes that VSELECT needs to be split, because the type is to wide for the given target. The same does not always apply to SETCC, because less space is required to encode the result of a comparison. As a result VSELECT is split and SETCC is unrolled into scalar comparisons. This commit fixes the issue by checking for VSELECT-SETCC patterns in the DAG Combiner. If a matching pattern is found, then the result mask of SETCC is promoted to the expected vector mask for the given target. This mask has usually te same size as the VSELECT return type (except for Intel KNL). Now the type legalizer will split both VSELECT and SETCC. This allows the following X86 DAG Combine code to sucessfully detect the MIN/MAX pattern. This fixes PR16695, PR17002, and <rdar://problem/14594431>. llvm-svn: 191130
-
Eric Christopher authored
info finalization to greatly reduce the number of fixups that the assembler has to handle in order to improve compile time. llvm-svn: 191119
-
Eric Christopher authored
to further work. llvm-svn: 191113
-
- Sep 20, 2013
-
-
Andrew Trick authored
The global registry is used to allow command line override of the scheduler selection, but does not work well as the normal selection API. For example, the same LLVM process should be able to target multiple targets or subtargets. llvm-svn: 191071
-
David Blaikie authored
DebugInfo: GDBIndexEntry*String conversion functions now return const char* for easy llvm::formating This was previously invoking UB by passing a user-defined type to format. Thanks to Jordan Rose for pointing this out. llvm-svn: 191060
-
David Blaikie authored
These violations were introduced in r191049 llvm-svn: 191059
-
Richard Mitton authored
llvm-svn: 191052
-
Andrew Trick authored
This was an experimental scheduler a year ago. It's now used by several subtargets, both in-order and out-of-order, and it is about to be enabled by default for x86 and armv7. It will be the new GenericScheduler for subtargets that don't provide their own SchedulingStrategy. llvm-svn: 191051
-
David Blaikie authored
llvm-svn: 191050
-
Kai Nacke authored
C-like languages promote types like unsigned short to unsigned int before performing an arithmetic operation. Currently the rotate matcher in the DAGCombiner does not consider this situation. This commit extends the DAGCombiner in the way that the pattern (or (shl ([az]ext x), (*ext y)), (srl ([az]ext x), (*ext (sub 32, y)))) is folded into ([az]ext (rotl x, y)) The matching is restricted to aext and zext because in this cases the upper bits are either undefined or known. Test case is included. This fixes PR16726. llvm-svn: 191049
-
Kai Nacke authored
There is a buildbot failure. Need to investigate this. llvm-svn: 191048
-
Kai Nacke authored
C-like languages promote types like unsigned short to unsigned int before performing an arithmetic operation. Currently the rotate matcher in the DAGCombiner does not consider this situation. This commit extends the DAGCombiner in the way that the pattern (or (shl ([az]ext x), (*ext y)), (srl ([az]ext x), (*ext (sub 32, y)))) is folded into ([az]ext (rotl x, y)) The matching is restricted to aext and zext because in this cases the upper bits are either undefined or known. Test case is included. This fixes PR16726. llvm-svn: 191045
-
David Blaikie authored
llvm-svn: 191043
-
- Sep 19, 2013
-
-
David Blaikie authored
Based on code review feedback from Eric Christopher, unshifting these constants as they can appear in the gdb_index itself, shifted a further 24 bits. This means that keeping them preshifted is a bit inflexible, so let's not do that. Given the motivation, wrap up some nicer enums, more type safety, and some utility functions. llvm-svn: 191035
-
David Blaikie authored
Names open to bikeshedding. Could switch back to the constants being unshifted, but this way seems a bit easier to work with. llvm-svn: 191025
-
David Blaikie authored
llvm-svn: 191020
-
David Blaikie authored
llvm-svn: 191018
-
Benjamin Kramer authored
DAGCombiner: Don't fold vector muls with constants that look like a splat of a power of 2 but differ in bit width. PR17283. llvm-svn: 191000
-
Adrian Prantl authored
Use the DIVariable::isIndirect() flag set by the frontend instead of guessing whether to set the machine location's indirection bit. Paired commit with CFE. llvm-svn: 190961
-
- Sep 17, 2013
-
-
Arnold Schwaighofer authored
Upcoming SLP vectorization improvements will want to be able to estimate costs of horizontal reductions. Add infrastructure to support this. We model reductions as a series of (shufflevector,add) tuples ultimately followed by an extractelement. For example, for an add-reduction of <4 x float> we could generate the following sequence: (v0, v1, v2, v3) \ \ / / \ \ / + + (v0+v2, v1+v3, undef, undef) \ / ((v0+v2) + (v1+v3), undef, undef) %rdx.shuf = shufflevector <4 x float> %rdx, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef> %bin.rdx = fadd <4 x float> %rdx, %rdx.shuf %rdx.shuf7 = shufflevector <4 x float> %bin.rdx, <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef> %bin.rdx8 = fadd <4 x float> %bin.rdx, %rdx.shuf7 %r = extractelement <4 x float> %bin.rdx8, i32 0 This commit adds a cost model interface "getReductionCost(Opcode, Ty, Pairwise)" that will allow clients to ask for the cost of such a reduction (as backends might generate more efficient code than the cost of the individual instructions summed up). This interface is excercised by the CostModel analysis pass which looks for reduction patterns like the one above - starting at extractelements - and if it sees a matching sequence will call the cost model interface. We will also support a second form of pairwise reduction that is well supported on common architectures (haddps, vpadd, faddp). (v0, v1, v2, v3) \ / \ / (v0+v1, v2+v3, undef, undef) \ / ((v0+v1)+(v2+v3), undef, undef, undef) %rdx.shuf.0.0 = shufflevector <4 x float> %rdx, <4 x float> undef, <4 x i32> <i32 0, i32 2 , i32 undef, i32 undef> %rdx.shuf.0.1 = shufflevector <4 x float> %rdx, <4 x float> undef, <4 x i32> <i32 1, i32 3, i32 undef, i32 undef> %bin.rdx.0 = fadd <4 x float> %rdx.shuf.0.0, %rdx.shuf.0.1 %rdx.shuf.1.0 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef> %rdx.shuf.1.1 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef> %bin.rdx.1 = fadd <4 x float> %rdx.shuf.1.0, %rdx.shuf.1.1 %r = extractelement <4 x float> %bin.rdx.1, i32 0 llvm-svn: 190876
-
Serge Pavlov authored
llvm-svn: 190866
-
Quentin Colombet authored
When a truncate node defines a legal vector type but uses an illegal vector type, the legalization process was splitting the vector until <1 x vector> type, but then it was failing to scalarize the node because it did not know how to handle TRUNCATE. <rdar://problem/14989896> llvm-svn: 190830
-
rdar://problem/14990587Adrian Prantl authored
A DBG_VALUE is register-indirect iff the first operand is a register _and_ the second operand is an immediate. llvm-svn: 190821
-
Jakub Staszak authored
llvm-svn: 190813
-