llvm-svn: 105987

containing the target address, an input, into an output.  I don't
think this actually broke anything on x86 (it does on ARM), but
it's wrong.

llvm-svn: 105986

the combined load/store instruction. rdar://7797940

llvm-svn: 105982

immediate" operands.  These functions have so far only been used for VMOV
but they also apply to other NEON instructions with modified immediate
operands.  No functional changes.

llvm-svn: 105969

Make sure to skip the dbg_value instructions when moving dups out of the
diamond. rdar://7797940

llvm-svn: 105965

- Rename ExactHazardRecognizer to PostRAHazardRecognizer and move its header to include to allow targets to extend it.

llvm-svn: 105959

llvm-svn: 105955

symbols as declarations in the X86 backend.  This would manifest
on darwin x86-32 as errors like this with -fvisibility=hidden:

symbol '__ZNSbIcED1Ev' can not be undefined in a subtraction expression

This fixes PR7353.

llvm-svn: 105954

fixes PR7356.

llvm-svn: 105950

llvm-svn: 105943

llvm-svn: 105942

more clear what exactly is missing.

llvm-svn: 105934

llvm-svn: 105914

llvm-svn: 105900

function name, patch by Yuri

llvm-svn: 105887

llvm-svn: 105878

llvm-svn: 105876

llvm-svn: 105873

clean-up to a catch-all after inlining, take into account that there could be
filter IDs as well. The presence of filters don't mean that the selector catches
anything. It's just metadata information.

llvm-svn: 105872

llvm-svn: 105870

Handle OpSize TSFlag for AVX

llvm-svn: 105869

llvm-svn: 105862

llvm-svn: 105861

llvm-svn: 105860

Introduce the VEX_X field

llvm-svn: 105859

i64 and f64 types, but now it also handle Neon vector types, so the f64 result
of VMOVDRR may need to be converted to a Neon type.  Radar 8084742.

llvm-svn: 105845

the machine instruction representation of the immediate value to be encoded
into an integer with similar fields as the actual VMOV instruction.  This makes
things easier for the disassembler, since it can just stuff the bits into the
immediate operand, but harder for the asm printer since it has to decode the
value to be printed.  Testcase for the encoding will follow later when MC has
more support for ARM.

llvm-svn: 105836

llvm-svn: 105828

llvm-svn: 105827

warnings with gcc-4.6, by not setting bits when the result is not
used.

llvm-svn: 105790

llvm-svn: 105775

llvm-svn: 105774

dbg_value immediately follows a sequence of ldr/str instructions that should
be combined into an ldm/stm and is the last instruction in the block, then
combine may end up being skipped.

llvm-svn: 105758

This is a bit of a hack to make inline asm look more like call instructions.
It would be better to produce correct dead flags during isel.

llvm-svn: 105749

Allow target to place 2-address pass inserted copies in better spots. Thumb2 will use this to try to avoid breaking up IT blocks.

llvm-svn: 105745

   %reg1025 = <sext> %reg1024
    ...
   %reg1026 = SUBREG_TO_REG 0, %reg1024, 4

into this:

   %reg1025 = <sext> %reg1024
    ...
   %reg1027 = EXTRACT_SUBREG %reg1025, 4
   %reg1026 = SUBREG_TO_REG 0, %reg1027, 4

The problem here is that SUBREG_TO_REG is there to assert that an implicit zext
occurs. It doesn't insert a zext instruction. If we allow the EXTRACT_SUBREG
here, it will give us the value after the <sext>, not the original value of
%reg1024 before <sext>.

llvm-svn: 105741

llvm-svn: 105740

Pulled CodeMetrics out of InlineCost.h and made it a bit more general, so it can be reused from PartialSpecializationCost

llvm-svn: 105725

We default to inserting to lane 0.

llvm-svn: 105722

random load/store, rather than crashing llc.

llvm-svn: 105710