by having X86DAGToDAGISel::SelectAddr get passed in the parent node
of the operand match (the load/store/atomic op) and having it get
the address space from that, instead of having special FS/GS addr
mode operations that require duplicating the entire instruction set
to support.

This makes FS and GS relative accesses *far* more predictable and
work much better.  It also simplifies the X86 backend a bit, more
to come.

There is still a pending issue with nodes like ISD::PREFETCH and
X86ISD::FLD, which really should be MemSDNode's but aren't.

llvm-svn: 114491

the predicate to discover the number of sign bits.  Enhance X86's target lowering to provide
a useful response to this query.

llvm-svn: 114473

passed the root of the match, even though only a few patterns
actually needed this (one in X86, several in ARM [which should
be refactored anyway], and some in CellSPU that I don't feel 
like detangling).   Instead of requiring all ComplexPatterns to
take the dead root, have targets opt into getting the root by
putting SDNPWantRoot on the ComplexPattern.

llvm-svn: 114471

llvm-svn: 114468

llvm-svn: 114463

(sbbl x, x) sets the registers to 0 or ~0.  Combined with two's complement arithmetic, we can fold
the intermediate AND and the ADD into a single SUB.

This fixes <rdar://problem/8449754>.

llvm-svn: 114460

llvm-svn: 114453

SelectionDAG::getExtLoad overload, and eliminate it.

llvm-svn: 114446

llvm-svn: 114410

"getFixedStack" on the MachinePointerInfo class.  While
this isn't the problem I'm setting out to solve, it is the
right way to eliminate PseudoSourceValue, so lets go with it.

llvm-svn: 114406

of the getLoad methods.  This fixes at least one bug where an incorrect
svoffset is passed in (a potential combiner-aa miscompile).

llvm-svn: 114404

into non-segment-relative copies.

llvm-svn: 114402

instead of srcvalue/offset pairs.  This corrects SV info for mem 
operations whose size is > 32-bits.

llvm-svn: 114401

llvm-svn: 114391

For now, just disable folding the load into the call.

llvm-svn: 114386

llvm-svn: 114297

This fixes rdar://8396318.

llvm-svn: 114201

What a weird instruction.

llvm-svn: 114190

llvm-svn: 114116

wraps up r8418316

llvm-svn: 113949

for call.  Add this.

llvm-svn: 113948

even in 64-bit mode apparently.

llvm-svn: 113945

add sldt GR32, which isn't documented in the intel manual
but which gas accepts.  Part of rdar://8418316

llvm-svn: 113938

llvm-svn: 113937

llvm-svn: 113936

version because it adds a prefix and makes even less sense
than the other broken forms.  This wraps up rdar://8431422

llvm-svn: 113932

llvm-svn: 113930

rdar://8431422

llvm-svn: 113929

instead of crashing.  This fixes:
rdar://8431815 - crash when invalid operand is one that isn't present

llvm-svn: 113921

llvm-svn: 113915

This fixes PR8114

llvm-svn: 113894

This reverts commit r113632

Conflicts:

	cmake/modules/AddLLVM.cmake

llvm-svn: 113819

v8i16 is not an MMX type; put it where it belongs.

llvm-svn: 113785

llvm-svn: 113766

llvm-svn: 113693

llvm-svn: 113692

This fixes rdar://8408129 - pushfd and popfd get invalid instruction mnemonic errors

llvm-svn: 113690

llvm-svn: 113689

the end of the line on a parser error, allowing skipping to happen
for syntactic errors but not for semantic errors.  Before we would
miss emitting a diagnostic about the second line, because we skipped
it due to the semantic error on the first line:

  foo %eax
  bar %al

This fixes rdar://8414033 - llvm-mc ignores lines after an invalid instruction mnemonic errors

llvm-svn: 113688

llvm-svn: 113632