- Oct 05, 2011
-
-
Jakob Stoklund Olesen authored
For example: %vreg10:dsub_0<def,undef> = COPY %vreg1 %vreg10:dsub_1<def> = COPY %vreg2 is rewritten as: %D2<def> = COPY %D0, %Q1<imp-def> %D3<def> = COPY %D1, %Q1<imp-use,kill>, %Q1<imp-def> The first COPY doesn't care about the previous value of %Q1, so it doesn't read that register. The second COPY is a partial redefinition of %Q1, so it implicitly kills and redefines that register. This makes it possible to recognize instructions that can harmlessly clobber the full super-register. The write and don't read the super-register. llvm-svn: 141139
-
Jakob Stoklund Olesen authored
RegisterCoalescer can create sub-register defs when it is joining a register with a sub-register. Add <undef> flags to these new sub-register defs where appropriate. llvm-svn: 141138
-
Owen Anderson authored
Teach the MC to output code/data region marker labels in MachO and ELF modes. These are used by disassemblers to provide better disassembly, particularly on targets like ARM Thumb that like to intermingle data in the TEXT segment. llvm-svn: 141135
-
Bill Wendling authored
llvm-svn: 141125
-
- Oct 04, 2011
-
-
Jakob Stoklund Olesen authored
The <undef> flag says that a MachineOperand doesn't read its register, or doesn't depend on the previous value of its register. A full register def never depends on the previous register value. A partial register def may depend on the previous value if it is intended to update part of a register. For example: %vreg10:dsub_0<def,undef> = COPY %vreg1 %vreg10:dsub_1<def> = COPY %vreg2 The first copy instruction defines the full %vreg10 register with the bits not covered by dsub_0 defined as <undef>. It is not considered a read of %vreg10. The second copy modifies part of %vreg10 while preserving the rest. It has an implicit read of %vreg10. This patch adds a MachineOperand::readsReg() method to determine if an operand reads its register. Previously, this was modelled by adding a full-register <imp-def> operand to the instruction. This approach makes it possible to determine directly from a MachineOperand if it reads its register. No scanning of MI operands is required. llvm-svn: 141124
-
Bill Wendling authored
llvm-svn: 141050
-
Bill Wendling authored
llvm-svn: 141040
-
- Oct 03, 2011
-
-
Bill Wendling authored
Move the grabbing of the jump buffer into the caller function, eliminating the need for returning a std::pair. llvm-svn: 141026
-
Eric Christopher authored
llvm-svn: 141005
-
Eric Christopher authored
llvm-svn: 141004
-
- Oct 01, 2011
-
-
Nadav Rotem authored
Moved type construction out of the loop and added an assert on the legality of the type. Formatted lines to the 80 char limit. llvm-svn: 140952
-
Bill Wendling authored
and the alignment is 0 (i.e., it's defined globally in one file and declared in another file) it could get an alignment which is larger than the ABI allows for that type, resulting in aligned moves being used for unaligned loads. For instance, in file A.c: struct S s; In file B.c: struct { // something long }; extern S s; void foo() { struct S p = s; // ... } this copy is a 'memcpy' which is turned into a series of 'movaps' instructions on X86. But this is wrong, because 'struct S' has alignment of 4, not 16. llvm-svn: 140902
-
Nick Lewycky authored
llvm-svn: 140899
-
Jakob Stoklund Olesen authored
It will soon need the context. llvm-svn: 140896
-
- Sep 30, 2011
-
-
Torok Edwin authored
thanks to Duncan. llvm-svn: 140850
-
Torok Edwin authored
This helps with porting code from 2.9 to 3.0 as TargetSelect.h changed location, and if you include the old one by accident you will trigger this assert. llvm-svn: 140848
-
- Sep 29, 2011
-
-
Eli Friedman authored
Clean up uses of switch instructions so they are not dependent on the operand ordering. Patch by Stepan Dyatkovskiy. llvm-svn: 140803
-
Duncan Sands authored
llvm-svn: 140784
-
Jakob Stoklund Olesen authored
llvm-svn: 140767
-
Eric Christopher authored
llvm-svn: 140745
-
Jakob Stoklund Olesen authored
The function needs to scan the implicit operands anyway, so no performance is won by caching the number of implicit operands added to an instruction. This also fixes a bug when adding operands after an implicit operand has been added manually. The NumImplicitOps count wasn't kept up to date. MachineInstr::addOperand() will now consistently place all explicit operands before all the implicit operands, regardless of the order they are added. It is possible to change an MI opcode and add additional explicit operands. They will be inserted before any existing implicit operands. The only exception is inline asm instructions where operands are never reordered. This is because of a hack that marks explicit clobber regs on inline asm as <implicit-def> to please the fast register allocator. This hack can go away when InstrEmitter and FastIsel can add exact <dead> flags to physreg defs. llvm-svn: 140744
-
- Sep 28, 2011
-
-
Bill Wendling authored
Upon further review, most of the EH code should remain written at the IR level. The part which breaks SSA form is the dispatch table, so that part will be moved to the back-end. llvm-svn: 140730
-
Duncan Sands authored
when there is both a catch and a cleanup. Correct the comment. llvm-svn: 140686
-
Bill Wendling authored
llvm-svn: 140678
-
Bill Wendling authored
llvm-svn: 140677
-
Bill Wendling authored
This intrinsic is used to pass the index of the function context to the back-end for further processing. The back-end is in charge of filling in the rest of the entries. llvm-svn: 140676
-
Bill Wendling authored
The DWARF exception pass uses the call site information, which is set up here. A pre-RA pass is too late for it to use this information. So create and setup the function context here, and then insert the call site values here (and map the call sites for the DWARF EH pass). This is simpler than the original pass, and doesn't make the CFG lose its SSA-ness. It's a win-win-win-win-lose-win-win situation. llvm-svn: 140675
-
Bill Wendling authored
We may need an SjLj EH preparation pass for some call site information, at least in the short term. llvm-svn: 140674
-
Jakob Stoklund Olesen authored
No functional change intended. llvm-svn: 140664
-
Jakob Stoklund Olesen authored
I'll clean up the source in the next commit. llvm-svn: 140663
-
Bill Wendling authored
current IR-level pass. The old SjLj EH pass has some problems, especially with the new EH model. Most significantly, it violates some of the new restrictions the new model has. For instance, the 'dispatch' table wants to jump to the landing pad, but we cannot allow that because only an invoke's unwind edge can jump to a landing pad. This requires us to mangle the code something awful. In addition, we need to keep the now dead landingpad instructions around instead of CSE'ing them because the DWARF emitter uses that information (they are dead because no control flow edge will execute them - the control flow edge from an invoke's unwind is superceded by the edge coming from the dispatch). Basically, this pass belongs not at the IR level where SSA is king, but at the code-gen level, where we have more flexibility. llvm-svn: 140646
-
- Sep 27, 2011
-
-
Cameron Zwarich authored
a suboptimal schedule. llvm-svn: 140643
-
Jim Grosbach authored
Naming conventions consistency. No functional change. llvm-svn: 140636
-
Nadav Rotem authored
Add a new method: getAnyExtOrTrunc and use it to replace the manual check. llvm-svn: 140603
-
Nadav Rotem authored
while the decision is to bit-pack small values. llvm-svn: 140601
-
- Sep 26, 2011
-
-
James Molloy authored
Fix emission of debug data for global variables. getContext() on DIGlobalVariables is not valid any more. llvm-svn: 140539
-
- Sep 25, 2011
-
-
Jakob Stoklund Olesen authored
Many targets use pseudo instructions to help register allocation. Like the COPY instruction, these pseudos can be expanded after register allocation. The early expansion can make life easier for PEI and the post-ra scheduler. This patch adds a hook that is called for all remaining pseudo instructions from the ExpandPostRAPseudos pass. llvm-svn: 140472
-
Nadav Rotem authored
SDNodes may return values which are wider than the incoming element types. In this patch we fix the integer promotion of these nodes. Fixes spill-q.ll when running -promote-elements. llvm-svn: 140471
-
Jakob Stoklund Olesen authored
No functional change intended. llvm-svn: 140470
-
Jakob Stoklund Olesen authored
I'll fix the file contents in the next commit. This pass is currently expanding the COPY and SUBREG_TO_REG pseudos. I am going to add a hook so targets can expand more pseudo-instructions after register allocation. Many targets have pseudo-instructions that assist the register allocator. They can be expanded after register allocation, before PEI and PostRA scheduling. llvm-svn: 140469
-