mode, and "ld64" (the default linker) falls back to it in -static
mode.

llvm-svn: 77334

llvm-svn: 77329

llvm-svn: 77326

llvm-svn: 77305

llvm-svn: 77301

- This change also makes it possible to switch between ARM / Thumb on a
  per-function basis.
- Fixed thumb2 routine which expand reg + arbitrary immediate. It was using
  using ARM so_imm logic.
- Use movw and movt to do reg + imm when profitable.
- Other code clean ups and minor optimizations.

llvm-svn: 77300

llvm-svn: 77295

it is highly specific to the object file that will be generated in the end,
this introduces a new TargetLoweringObjectFile interface that is implemented
for each of ELF/MachO/COFF/Alpha/PIC16 and XCore.

Though still is still a brutal and ugly refactoring, this is a major step
towards goodness.

This patch also:
1. fixes a bunch of dangling pointer problems in the PIC16 backend.
2. disables the TargetLowering copy ctor which PIC16 was accidentally using.
3. gets us closer to xcore having its own crazy target section flags and
   pic16 not having to shadow sections with its own objects.
4. fixes wierdness where ELF targets would set CStringSection but not
   CStringSection_.  Factor the code better.
5. fixes some bugs in string lowering on ELF targets.

llvm-svn: 77294

llvm-svn: 77293

llvm-svn: 77275

 - My DFS traversal of LLVM is, at least for now, nearly complete! :)

llvm-svn: 77258

MCSections soon instead of Section for all targets, and we need something to
own them.

llvm-svn: 77252

llvm-svn: 77247

Remove TPat. No patterns depend on just isThumb(). Must use either T1Pat (isThumb1Only()) or T2Pat (is Thumb2).

llvm-svn: 77242

implementations that need it, rearrange ELFTAI.

llvm-svn: 77236

llvm-svn: 77233

llvm-svn: 77231

convertToThreeAddress can't handle Thumb2 instructions (which don't have same address mode as ARM instructions).

llvm-svn: 77230

llvm-svn: 77227

llvm-svn: 77222

llvm-svn: 77221

This also fixes potential problems in ARMBaseInstrInfo routines not recognizing thumb1 instructions when 32-bit and 16-bit instructions mix.

llvm-svn: 77218

llvm-svn: 77217

Some libcall names are same, so they were getting printed twice.

llvm-svn: 77215

not in mergable

llvm-svn: 77210

header even though there is only one COFF target.

llvm-svn: 77204

llvm-svn: 77203

llvm-svn: 77202

llvm-svn: 77201

llvm-svn: 77199

llvm-svn: 77198

llvm-svn: 77197

should know about them.  PECoff doesn't share these, and I want all sections
to be created by object-file-specific code.

llvm-svn: 77196

llvm-svn: 77191

instead.

llvm-svn: 77186

instead and drive things based off of that.

llvm-svn: 77184

llvm-svn: 77182

llvm-svn: 77181

llvm-svn: 77179

fixed incorrect lowering of ISD::SUB node. SUB has only one result value.
It wasn't caught during tests because we never got a sub generated, (i8 was always getting promoted to int, which in turn was broken into subc/sube). Though the optimizer leaves an i8 sub now. 

llvm-svn: 77178