llvm-svn: 106119

llvm-svn: 106117

llvm-svn: 106102

The memcmp will be optimized further and even the pathological case
'strstr(x, "x") == x' generates optimal code now.

llvm-svn: 106097

Make post-ra scheduling, anti-dep breaking, and register scavenger (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler.

llvm-svn: 106091

llvm-svn: 106088

This speeds up local variable handling in DwarfDebug.

llvm-svn: 106075

llvm-svn: 106073

llvm-svn: 106072

will conflict with another live range. The place which creates this scenerio is
the code in X86 that lowers a select instruction by splitting the MBBs. This
eliminates the need to check from the bottom up in an MBB for live pregs.

llvm-svn: 106066

a relative address.

llvm-svn: 106064

llvm-svn: 106063

llvm-svn: 106062

llvm-svn: 106058

llvm-svn: 106057

llvm-svn: 106056

llvm-svn: 106054

call must not be callee-saved; following x86, add a new
regclass to represent this.  Also fixes a couple of bugs.
Still disabled by default; Thumb doesn't work yet.

llvm-svn: 106053

Please use the fast allocator instead.

llvm-svn: 106051

flag argument to addReg is not the same format as flags attached
to MachineOperand, although both have the same info.  I don't
think this actually mattered; the bootstrap failure did not
reproduce on the next run anyway.

llvm-svn: 106049

portability to Solaris 10, which apparently doesn't support
[ foo -ot bar ]

llvm-svn: 106048

llvm-svn: 106047

llvm-svn: 106041

llvm-svn: 106038

no tolerance is set.

llvm-svn: 106033

  1..19 ok
to
  1..20 o k
(yes, the odd space is necessary).

llvm-svn: 106032

Nelson Elhage!

llvm-svn: 106031

llvm-svn: 106030

for the linux targets.

llvm-svn: 106029

of base class slicing bugs reported on irc

llvm-svn: 106028

llvm-svn: 106027

llvm-svn: 106024

SimpleRegisterCoalescing::JoinIntervals() uses CoalescerPair to determine if a
copy is coalescable, and in very rare cases it can return true where LHS is not
live - the coalescable copy can come from an alias of the physreg in LHS.

llvm-svn: 106021

llvm-svn: 106015

llvm-svn: 106009

combined to an insert_subreg, i.e., where the destination register is larger
than the source.  We need to check that the subregs can be composed for that
case in a symmetrical way to the case when the destination is smaller.

llvm-svn: 106004

Early clobbers defining a virtual register were first alocated to a physreg and
then processed as a physreg EC, spilling the virtreg.

This fixes PR7382.

llvm-svn: 105998

Given a copy instruction, CoalescerPair can determine which registers to
coalesce in order to eliminate the copy. It deals with all the subreg fun to
determine a tuple (DstReg, SrcReg, SubIdx) such that:

- SrcReg is a virtual register that will disappear after coalescing.
- DstReg is a virtual or physical register whose live range will be extended.
- SubIdx is 0 when DstReg is a physical register.
- SrcReg can be joined with DstReg:SubIdx.

CoalescerPair::isCoalescable() determines if another copy instruction is
compatible with the same tuple. This fixes some NEON miscompilations where
shuffles are getting coalesced as if they were copies.

The CoalescerPair class will replace a lot of the spaghetti logic in JoinCopy
later.

llvm-svn: 105997

llvm-svn: 105994

replacing the overly conservative checks that I had introduced recently to
deal with correctness issues.  This makes a pretty noticable difference
in our testcases where reg_sequences are used.  I've updated one test to
check that we no longer emit the unnecessary subreg moves.

llvm-svn: 105991