Fixed spilling of %fcc[0-3] which are part of %fsr.

(2) Moved some machine-independent reg-class code to class TargetRegInfo
    from SparcReg{Class,}Info.

(3) Renamed MachienOperand::opIsDef to MachineOperand::opIsDefOnly()
    and related functions and flags.  Fixed several bugs where only
    "isDef" was being checked, not "isDefAndUse".

llvm-svn: 6341

llvm-svn: 6131

* *** Finally mark values that are inputs to PHIs as killed when appropriate.
   This should make the generated code quite a bit better.  For example, the
   local-ra will not have to spill PHI inputs at the end of predecessor BB's
   anymore.

llvm-svn: 6117

llvm-svn: 6116

llvm-svn: 6112

* Update LiveVar info better, fixing bug: Jello/2003-05-11-PHIRegAllocBug.ll

llvm-svn: 6110

llvm-svn: 5326

llvm-svn: 5272

llvm-svn: 5262