Commits · da0192d72bc173281e97a92cb516d36572a0a74c · Roger Ferrer / llvm-epi-0.8

Aug 12, 2011
- Remove the InterferenceResult class. · da0192d7
  Jakob Stoklund Olesen authored Aug 11, 2011
```
llvm-svn: 137381
```
  da0192d7
- Eliminate the last use of InterferenceResult. · cd14efae
  Jakob Stoklund Olesen authored Aug 11, 2011
```
The Query class now holds two iterators instead of an InterferenceResult
instance. The iterators are used as bookmarks for repeated
collectInterferingVRegs calls.

llvm-svn: 137380
```
  cd14efae
- Enclose directive .cprestore with .set macro and nomacro to silence assembler · 79d60d0e
  Akira Hatanaka authored Aug 11, 2011
```
warning. 

llvm-svn: 137378
```
  79d60d0e
- Remove no-longer-true comments. These are for the assembler, also. · 37f7e6b2
  Jim Grosbach authored Aug 11, 2011
```
llvm-svn: 137375
```
  37f7e6b2
- ARM STRT assembly parsing and encoding. · e2594215
  Jim Grosbach authored Aug 11, 2011
```
llvm-svn: 137372
```
  e2594215
- Make the USAT16 operand decoder auto-generate-able. · eca346ee
  Owen Anderson authored Aug 11, 2011
```
llvm-svn: 137371
```
  eca346ee
- Add another accidentally omitted predicate operand. · ff0b4423
  Owen Anderson authored Aug 11, 2011
```
llvm-svn: 137370
```
  ff0b4423
- Add missing predicate operand on SMLA and friends. · 2f7aa733
  Owen Anderson authored Aug 11, 2011
```
llvm-svn: 137368
```
  2f7aa733
- ARM load shifted register pre-index fix shift value asm parser encoding. · a2b8b606
  Jim Grosbach authored Aug 11, 2011
```
llvm-svn: 137367
```
  a2b8b606
Aug 11, 2011
- Handle new register classes in Thumb2 mode. Should fix the ARM buildbots. · 12d13efa
  Owen Anderson authored Aug 11, 2011
```
llvm-svn: 137364
```
  12d13efa
- Making SEL decodings auto-generate-able. · f05e7448
  Owen Anderson authored Aug 11, 2011
```
llvm-svn: 137363
```
  f05e7448
- Add a dag combine to xform 256-bit shuffles into simple vector · 8fbf023c
  Bruno Cardoso Lopes authored Aug 11, 2011
```
inserts and extracts. This simple combine makes us generate only 1
instruction instead of 11 in the v8 case.

llvm-svn: 137362
```
  8fbf023c
- Tidy up comment. · 88981ff1
  Jim Grosbach authored Aug 11, 2011
```
llvm-svn: 137359
```
  88981ff1
- Fix decoding support for STREXD and LDREXD. · b685c9f0
  Owen Anderson authored Aug 11, 2011
```
llvm-svn: 137356
```
  b685c9f0
- Remove more dead code. · da4f0eb1
  Jakob Stoklund Olesen authored Aug 11, 2011
```
collectInterferingVRegs will be the primary function for interference
checks.

llvm-svn: 137354
```
  da4f0eb1
- ARM STRH assembly parsing and encoding. · d886f8cd
  Jim Grosbach authored Aug 11, 2011
```
llvm-svn: 137353
```
  d886f8cd
- Fix typos in comments, and delete an unused function. · 7e315fc3
  Dan Gohman authored Aug 11, 2011
```
llvm-svn: 137352
```
  7e315fc3
- Add isIndirectBranch flag. · 6d8c039a
  Akira Hatanaka authored Aug 11, 2011
```
llvm-svn: 137351
```
  6d8c039a
- Privatize an unused part of the LiveIntervalUnion::Query interface. · 75193367
  Jakob Stoklund Olesen authored Aug 11, 2011
```
No clients are iterating over interference overlaps.

llvm-svn: 137350
```
  75193367
- Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>. · 3a850f28
  Owen Anderson authored Aug 11, 2011
```
llvm-svn: 137347
```
  3a850f28
- Remove some dead code. · 05ff9d1f
  Jakob Stoklund Olesen authored Aug 11, 2011
```
The InterferenceResult iterator turned out to be less important than we
thought it would be.  LiveIntervalUnion clients want higher level
information, like the list of interfering virtual registers.

llvm-svn: 137346
```
  05ff9d1f
- Tidy up. Remove unused template parameter. · 2ea19d14
  Jim Grosbach authored Aug 11, 2011
```
llvm-svn: 137345
```
  2ea19d14
- Improve operand validation for Thumb2 addressing modes. · 887c0b13
  Owen Anderson authored Aug 11, 2011
```
llvm-svn: 137344
```
  887c0b13
- ARM STRD assembly parsing and encoding. · eb09f49a
  Jim Grosbach authored Aug 11, 2011
```
llvm-svn: 137342
```
  eb09f49a
- Fix for LoopInfo::updateUnloop. Remove subloop blocks from former · c12c30a6
  Andrew Trick authored Aug 11, 2011
```
ancestor loops.

I have a unit test that depends on scev-unroll, which unfortunately
isn't checked in. But I will check it in when I can.

llvm-svn: 137341
```
  c12c30a6
- Continue to tighten decoding by performing more operand validation. · 60663403
  Owen Anderson authored Aug 11, 2011
```
llvm-svn: 137340
```
  60663403
- Tidy up. · 1b0f7957
  Jim Grosbach authored Aug 11, 2011
```
llvm-svn: 137339
```
  1b0f7957
- ARM STRBT assembly parsing and encoding. · 2a50260f
  Jim Grosbach authored Aug 11, 2011
```
llvm-svn: 137337
```
  2a50260f
- ARM STR(immediate) assembly parsing and encoding. · d564bf31
  Jim Grosbach authored Aug 11, 2011
```
llvm-svn: 137331
```
  d564bf31
- Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases. · 3477f2ce
  Owen Anderson authored Aug 11, 2011
```
llvm-svn: 137325
```
  3477f2ce
- Fix PR10492 by teaching MOVHLPS and MOVLPS mask matching to be more strict. · 043c8208
  Bruno Cardoso Lopes authored Aug 11, 2011
```
llvm-svn: 137324
```
  043c8208
- Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC. · 0e15b48f
  Owen Anderson authored Aug 11, 2011
```
llvm-svn: 137323
```
  0e15b48f
- Correct immediate range for shifter operands. Patch by James Molloy, with... · e33c95d3
  Owen Anderson authored Aug 11, 2011
```
Correct immediate range for shifter operands.  Patch by James Molloy, with additional encoding fixes added by me.

llvm-svn: 137322
```
  e33c95d3
- Plug a memory leak. · fa7e6a54
  Benjamin Kramer authored Aug 11, 2011
```
llvm-svn: 137321
```
  fa7e6a54
- Improve error checking in the new ARM disassembler. Patch by James Molloy. · ed253852
  Owen Anderson authored Aug 11, 2011
```
llvm-svn: 137320
```
  ed253852
- ARM push of a single register encodes as pre-indexed STR. · 27ad83d8
  Jim Grosbach authored Aug 11, 2011
```
Per the ARM ARM, a 'push' of a single register encodes as an STR,
not an STM.

llvm-svn: 137318
```
  27ad83d8
- Cleanup. Another thorough review by Nick! · 266ab100
  Andrew Trick authored Aug 11, 2011
```
llvm-svn: 137317
```
  266ab100
- ARM pop of a single register encodes as post-indexed LDR. · 8ba76c6d
  Jim Grosbach authored Aug 11, 2011
```
Per the ARM ARM, a 'pop' of a single register encodes as an LDR,
not an LDM.

llvm-svn: 137316
```
  8ba76c6d
- Add a comment, per Bruno's CR. · efdd183f
  Nadav Rotem authored Aug 11, 2011
```
llvm-svn: 137313
```
  efdd183f
- [AVX] When joining two XMM registers into a YMM register, make sure that the · 61140e10
  Nadav Rotem authored Aug 11, 2011
```
lower XMM register gets in first. This will allow the SUBREG pattern to
elliminate the first vector insertion. 

llvm-svn: 137310
```
  61140e10