sharp all or nothing transition when one extra predecessor was added. Now
we still test first ones for merging.

llvm-svn: 132974

only if the number of packed elements is a power of two.
Bug found in Duncan's testcase.

llvm-svn: 132923

In particular, don't spill dirty registers only to satisfy a hint. It is
not worth it.

The attached test case provides an example where the fast allocator
would spill a register when other registers are available.

llvm-svn: 132900

llvm-svn: 132899

having.

llvm-svn: 132898

types such as i33 were rounded to i32. Originated from Duncan's testcase.

llvm-svn: 132893

Instead of scalarizing, and doing an element-by-element truncat, use vector
truncate.
Add support for scalarization of vectors:  i8 -> <1 x i1> (from Duncan's
testcase).

llvm-svn: 132892

Add a triple to the tests.

llvm-svn: 132885

llvm-svn: 132883

we try to branch to them.

Before we were creating successor lists with duplicated entries. Fixing that
found a bug in isBlockOnlyReachableByFallthrough that would causes it to
return the wrong answer for

-----------
...
jne foo
jmp bar

foo:
----------

llvm-svn: 132882

llvm-svn: 132872

llvm-svn: 132871

llvm-svn: 132863

llvm-svn: 132857

comment on their meaning.

llvm-svn: 132854

llvm-svn: 132853

llvm-svn: 132852

Thanks Bob Wilson for noticing it!

llvm-svn: 132851

and definitions when emitting global variables.  This was causing global 
declarations to be emitted as if they were definitions.
Fixes <rdar://problem/9429892>.

llvm-svn: 132825

llvm-svn: 132822

llvm-svn: 132821

With this I am able to bootstrap clang with early tail duplication enabled
for any small bb and setting tail-dup-size to a relatively large value(8) to
stress this code.

llvm-svn: 132816

llvm-svn: 132814

Change this DAGCombine to build AND of SHR instead of SHR of AND; this matches the ordering we prefer in instcombine.  Part of rdar://9562809.

The potential DAGCombine which enforces this more generally messes up some other very fragile patterns, so I'm leaving that alone, at least for now.

llvm-svn: 132809

eh edges. Swap the order of the checks to avoid it.

llvm-svn: 132806

llvm-svn: 132805

No functionality change.

llvm-svn: 132798

llvm-svn: 132776

llvm-svn: 132771

of the frame then increase the maximum alignment of the frame to
match.

Fixes PR6965

llvm-svn: 132764

No functional change.

Part of PR6965

llvm-svn: 132763

llvm-svn: 132751

llvm-svn: 132749

llvm-svn: 132748

operands to an early clobber register. This fixes <rdar://problem/9566076>.

llvm-svn: 132738

Fixes PR10095.

llvm-svn: 132735

I've been sitting on this long enough trying to find a test case. I
think the fix should go in now, but I'll keep working on the test case.

llvm-svn: 132701

When local live range splitting creates a live range with the same
number of instructions as the old range, mark it as RS_Local. When such
a range is seen again, require that it be split in a way that reduces
the number of instructions. That guarantees we are making progress while
still being able to perform 3 -> 2+3 splits as required by PR10070.

This also means that the PrevSlot map is no longer needed. This was also
used to estimate new spill weights, but that is no longer necessary
after slotIndexes::insertMachineInstrInMaps() got the extra Late
insertion argument.

llvm-svn: 132697

Only target-dependent hints require callbacks. The RCI allocation order
has CSR aliases last according to their order of appearance in the
getCalleeSavedRegs list. This can depend on the calling convention.

This way, AllocationOrder::next doesn't have to check for reserved
registers, and CSRs are always allocated last, even with weird calling
conventions.

llvm-svn: 132690

legalize SDNodes such as BUILD_VECTOR, EXTRACT_VECTOR_ELT, etc.

llvm-svn: 132689