immediate operands when they will fit into the using instruction.

llvm-svn: 84778

llvm-svn: 84751

llvm-svn: 84573

register-shifted-register instructions.  Patch by Johnny Chen.

llvm-svn: 84124

llvm-svn: 84009

Patch by Johnny Chen.

llvm-svn: 83983

llvm-svn: 83973

when loading from an invariant memory location.

llvm-svn: 83688

Patch by Johnny Chen.

llvm-svn: 83407

ld / st pairs, etc.

llvm-svn: 83197

Change ld/st multiples to explicitly model the writeback to base register. This fixes most of the -ldstopti-before-sched2 regressions.

llvm-svn: 83191

Patch by Sylvere Teissier.

llvm-svn: 83135

instruction. This makes it re-materializable.

Thumb2 will split it back out into two instructions so IT pass will generate the
right mask. Also, this expose opportunies to optimize the movw to a 16-bit move.

llvm-svn: 82982

Disable rematting of it for now.

llvm-svn: 82975

This should be better than single load from constpool.

llvm-svn: 82948

llvm-svn: 81310

llvm-svn: 80956

llvm-svn: 80699

llvm-svn: 80350

See http://llvm.org/PR4687 for more info and links.

llvm-svn: 80244

several things other than Neon vector lane numbers.  For inline assembly
operands with a "c" print code, check that they really are immediates.

llvm-svn: 79676

llvm-svn: 79436

llvm-svn: 78918

llvm-svn: 78908

llvm-svn: 78905

llvm-svn: 78904

Enhance the InstrStage object to enable the specification of an Itinerary with overlapping stages. The default is to maintain the current behavior that the "next" stage immediately follows the previous one.

llvm-svn: 78827

llvm-svn: 78806

the latter is capable of representing either a primitive or an extended type.

llvm-svn: 78713

and short. Well, it's kinda short. Definitely nasty and brutish.

The front-end generates the register/unregister calls into the SjLj runtime,
call-site indices and landing pad dispatch. The back end fills in the LSDA
with the call-site information provided by the front end. Catch blocks are
not yet implemented.

Built on Darwin and verified no llvm-core "make check" regressions.

llvm-svn: 78625

llvm-svn: 78610

'no_hash' modifier. Hopefully this will make Daniel happy :)

llvm-svn: 78514

llvm-svn: 78468

Add parameter to pattern classes to enable an itinerary to be specified for instructions. For now just use the existing itineraries or NoItinerary.

llvm-svn: 78321

Initial support for single-precision FP using NEON. Added "neonfp" attribute to enable. Added patterns for some binary FP operations.

llvm-svn: 78081

llvm-svn: 77507

- Darwin Thumb2 call clobbers r9.

llvm-svn: 77500

llvm-svn: 77422

In thumb2 mode, add pc is unpredictable. Use add + mov pc instead (that is until more optimization goes in).

llvm-svn: 77364

Before:
      adr r12, #LJTI3_0_0
      ldr pc, [r12, +r0, lsl #2]
LJTI3_0_0:
      .long    LBB3_24
      .long    LBB3_30
      .long    LBB3_31
      .long    LBB3_32

After:
      adr r12, #LJTI3_0_0
      add pc, r12, +r0, lsl #2
LJTI3_0_0:
      b.w    LBB3_24
      b.w    LBB3_30
      b.w    LBB3_31
      b.w    LBB3_32

This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
   (smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
   into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
   won't have to over-estimate the size.

Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.

llvm-svn: 77024