llvm-svn: 118926

to splitting the load/store pre/post indexed instructions into [r, r] and
[r, imm] forms.

llvm-svn: 118925

llvm-svn: 118907

llvm-svn: 118829

instructions.

llvm-svn: 118801

llvm-svn: 118794

llvm-svn: 118767

llvm-svn: 118761

llvm-svn: 118757

encoding bits.

llvm-svn: 118738

llvm-svn: 118736

llvm-svn: 118732

llvm-svn: 118730

llvm-svn: 118600

llvm-svn: 118513

llvm-svn: 118462

llvm-svn: 118457

an initial implementation and may change once reglists are fully fleshed out.

llvm-svn: 118390

Fix @llvm.prefetch isel. Selecting between pld / pldw using the first immediate rw. There is currently no intrinsic that matches to pli.

llvm-svn: 118237

Fix preload instruction isel. Only v7 supports pli, and only v7 with mp extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing.

llvm-svn: 118160

llvm-svn: 118152

    vldr.64 d1, [r0, #-32]

The problem was with how the addressing mode 5 encodes the offsets. This change
makes sure that the way offsets are handled in addressing mode 5 is consistent
throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue"
method into an "Imm12" and "addressing mode 5" version. But not to worry! The
majority of the duplicated code has been unified.

llvm-svn: 118144

parts. Represent the operation mode as an optional operand instead.
rdar://8614429

llvm-svn: 118137

ins/outs list that isn't specified by their asmstring.  Previously
the asmmatcher would just force a 0 register into it, which clearly
isn't right.  Mark a bunch of ARM instructions that use this as 
isCodeGenOnly.  Some of them are clearly pseudo instructions (like
t2TBB) others use a weird hasExtraSrcRegAllocReq thing that will
either need to be removed or the asmmatcher will need to be taught
about it (someday).

llvm-svn: 118119

with immediates up to 16-bits in size. The same logic is applied to other LDR
encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in
VLDR's case). Removing the "12" allows it to be more generic.

llvm-svn: 118094

llvm-svn: 118093

llvm-svn: 118029

llvm-svn: 117997

llvm-svn: 117984

This is another part of the fix for Radar 8599955.

llvm-svn: 117976

llvm-svn: 117929

got a dulicated line).

llvm-svn: 117860

llvm-svn: 117859

Instead of silently ignoring these instructions, emit a hard error and
force the target author to either refactor the target or mark the 
instruction 'isCodeGenOnly'.

Mark a few instructions in ARM and MBlaze as isCodeGenOnly the are 
doing this.

llvm-svn: 117858

There were a number of issues to fix up here:
* The "device" argument of the llvm.memory.barrier intrinsic should be
used to distinguish the "Full System" domain from the "Inner Shareable"
domain.  It has nothing to do with using DMB vs. DSB instructions.
* The compiler should never need to emit DSB instructions.  Remove the
ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB.
* Merge the separate DMB/DSB instructions for options only used for the
disassembler with the default DMB/DSB instructions.  Add the default
"full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum.
* Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement
a data memory barrier using the MCR instruction.
* Fix up encodings for these instructions (except MCR).
I also updated the tests and added a few new ones to check for DMB options
that were not currently being exercised.

llvm-svn: 117756

llvm-svn: 117753

encoder functions.

llvm-svn: 117738

the ARMExpandPseudos pass rather than during the asm lowering.

llvm-svn: 117714

llvm-svn: 117703

llvm-svn: 117702