Nothing fancy, just ask the target if any currently available base reg
is in range for the instruction under consideration and use the first one
that is. Placeholder ARM implementation simply returns false for now.

ongoing saga of rdar://8277890

llvm-svn: 111374

llvm-svn: 111366

the local block. Resolve references to those indices to a new base register.
For simplification and testing purposes, a new virtual base register is
allocated for each frame index being resolved. The result is truly horrible,
but correct, code that's good for exercising the new code paths.

Next up is adding thumb1 support, which should be very simple. Following that
will be adding base register re-use and implementing a reasonable ARM
heuristic for when a virtual base register should be generated at all.

llvm-svn: 111315

PR 7882.  Follows suggestion by Amaury Pouly, thanks.

llvm-svn: 111306

PHI elimination shouldn't require machineloopinfo since it's used at -O0. Move the requirement to LiveIntervalAnalysis instead. Note this does not change the number of times machineloopinfo is computed.

llvm-svn: 111285

llvm-svn: 111281

llvm-svn: 111274

whether to allocate a virtual frame base register to resolve the frame
index reference in it. Implement a simple version for ARM to aid debugging.

In LocalStackSlotAllocation, scan the function for frame index references
to local frame indices and ask the target whether to allocate virtual
frame base registers for any it encounters. Purely infrastructural for
debug output. Next step is to actually allocate base registers, then add
intelligent re-use of them.

rdar://8277890

llvm-svn: 111262

Move the decision logic whether it's a good idea to split a critical edge to clients. Also fixed an erroneous check. An edge is only a back edge when the from and to blocks are in the same loop.

llvm-svn: 111256

llvm-svn: 111250

llvm-svn: 111223

PHI elimination should not break back edge. It can cause some significant code placement issues. rdar://8263994

good:
LBB0_2:
  mov     r2, r0
  . . .
  mov     r1, r2
  bne     LBB0_2

bad:
LBB0_2:
  mov     r2, r0
  . . .
@ BB#3:
  mov     r1, r2
  b       LBB0_2

llvm-svn: 111221

llvm-svn: 111206

mapping. Have the local block track its alignment requirement, and then
apply that when the block itself is allocated. Previously, offsets could
get adjusted in PEI to be different, relative to one another, than the
block allocation thought they would be, which defeats the point of doing
the allocation this way. Continuing rdar://8277890

llvm-svn: 111197

emission.

llvm-svn: 111177

llvm-svn: 111164

llvm-svn: 111156

llvm-svn: 111063

experimental pass that allocates locals relative to one another before
register allocation and then assigns them to actual stack slots as a block
later in PEI. This will eventually allow targets with limited index offset
range to allocate additional base registers (not just FP and SP) to
more efficiently reference locals, as well as handle situations where
locals cannot be referenced via SP or FP at all (dynamic stack realignment
together with variable sized objects, for example). It's currently
incomplete and almost certainly buggy. Work in progress.

Disabled by default and gated via the -enable-local-stack-alloc command
line option.

rdar://8277890

llvm-svn: 111059

The earliestStart argument is entirely specific to linear scan allocation, and
can be easily calculated by RegAllocLinearScan.

Replace std::vector with SmallVector.

llvm-svn: 111055

When a live range is contained a single block, we can split it around
instruction clusters. The current approach is very primitive, splitting before
and after the largest gap between uses.

llvm-svn: 111043

llvm-svn: 111019

numbers match. The old check could accidentally leave holes in openli.

Also let useIntv add all ranges for the phi-def value inserted by
enterIntvAtEnd. This works as long at the value mapping is established in
enterIntvAtEnd.

llvm-svn: 110995

function to do it.

llvm-svn: 110994

This can happen if the original interval has been broken into two disconnected
parts. Ideally, we should be able to detect when the graph is disconnected and
create separate intervals, but that code is not implemented yet.

Example:

Two basic blocks are both branching to a loop header. Our interval is defined in
both basic blocks, and live into the loop along both edges.

We decide to split the interval around the loop. The interval is split into an
inside part and an outside part. The outside part now has two disconnected
segments, one in each basic block.

If we later decide to split the outside interval into single blocks, we get one
interval per basic block and an empty dupli for the remainder.

llvm-svn: 110976

split intervals. THis means the analysis can be used for multiple splits as long
as curli doesn't shrink.

llvm-svn: 110975

If a phi-def value were removed from the interval, the phi-kill flags are no
longer valid.

llvm-svn: 110949

llvm-svn: 110944

llvm-svn: 110940

Before spilling a live range, we split it into a separate range for each basic
block where it is used. That way we only get one reload per basic block if the
new smaller ranges can allocate to a register.

This type of splitting is already present in the standard spiller.

llvm-svn: 110934

llvm-svn: 110826

a register before checking if it was defined.

llvm-svn: 110733

operands. We don't currently have a hook to provide "the largest super class of
A where all registers' getSubReg(subidx) is valid and in B".

llvm-svn: 110730

llvm-svn: 110726

The live interval may be used for a spill slot as well, and that spill slot
could be shared by split registers. We cannot shrink it, even if we know the
current register won't need the spill slot in that range.

llvm-svn: 110721

llvm-svn: 110720

ARM testers.

llvm-svn: 110718

llvm-svn: 110712

When splitting a live range, the new registers have fewer uses and the
permissible register class may be less constrained. Recompute the register class
constraint from the uses of new registers created for a split. This may let them
be allocated from a larger set, possibly avoiding a spill.

llvm-svn: 110703

during live range splitting.

llvm-svn: 110686