Stack is formed improperly for long structures passed as byval arguments for
EABI mode.

If we took AAPCS reference, we can found the next statements:

A: "If the argument requires double-word alignment (8-byte), the NCRN (Next
Core Register Number) is rounded up to the next even register number." (5.5
Parameter Passing, Stage C, C.3).

B: "The alignment of an aggregate shall be the alignment of its most-aligned
component." (4.3 Composite Types, 4.3.1 Aggregates).

So if we have structure with doubles (9 double fields) and 3 Core unused
registers (r1, r2, r3): caller should use r2 and r3 registers only.
Currently r1,r2,r3 set is used, but it is invalid.

Callee VA routine should also use r2 and r3 regs only. All is ok here. This
behaviour is guessed by rounding up SP address with ADD+BFC operations.

Fix:
Main fix is in ARMTargetLowering::HandleByVal. If we detected AAPCS mode and
8 byte alignment, we waste odd registers then.

P.S.:
I also improved LDRB_POST_IMM regression test. Since ldrb instruction will
not generated by current regression test after this patch. 

llvm-svn: 166018

Original message:

The attached is the fix to radar://11663049. The optimization can be outlined by following rules:

   (select (x != c), e, c) -> select (x != c), e, x),
   (select (x == c), c, e) -> select (x == c), x, e)
where the <c> is an integer constant.

 The reason for this change is that : on x86, conditional-move-from-constant needs two instructions;
however, conditional-move-from-register need only one instruction.

  While the LowerSELECT() sounds to be the most convenient place for this optimization, it turns out to be a bad place. The reason is that by replacing the constant <c> with a symbolic value, it obscure some instruction-combining opportunities which would otherwise be very easy to spot. For that reason, I have to postpone the change to last instruction-combining phase.

  The change passes the test of "make check-all -C <build-root/test" and "make -C project/test-suite/SingleSource".

Original message since r165661:

My previous change has a bug: I negated the condition code of a CMOV, and go ahead creating a new CMOV using the *ORIGINAL* condition code.

llvm-svn: 166017

llvm-svn: 166016

Fix a bug in the set(I,E)/reset(I,E) methods that I recently added.  The boundary condition for checking if I and E were in the same word were incorrect, and, beyond that, the mask computation was not using a wide enough constant.

llvm-svn: 166015

llvm-svn: 166014

llvm-svn: 166013

llvm-svn: 166012

llvm-svn: 166011

Use the Attributes::get method which takes an AttrVal value directly to simplify the code a bit. No functionality change.

llvm-svn: 166010

Use the Attributes::get method which takes an AttrVal value directly to simplify the code a bit. No functionality change.

llvm-svn: 166009

llvm-svn: 166008

llvm-svn: 166007

llvm-svn: 166006

must push something on the stack for a function call or not.  In
x86, the stack pointer is decremented when the caller's pc is saved
on the stack.  In arm, the stack pointer and frame pointer don't
necessarily have to change for a function call, although most
functions need to use some stack space during their execution.

Use this information in the RegisterContextLLDB to detect invalid 
unwind scenarios more accurately.

<rdar://problem/12348574>

llvm-svn: 166005

llvm-svn: 166004

llvm-svn: 166003

Follow-up to r165838, which fixed a potential crash.

llvm-svn: 166002

This is a medium term workaround until we have a more robust solution
in the form of a register liveness utility for postRA passes.

llvm-svn: 166001

Patch from Matt Kopec <matt.kopec@intel.com> to fix the problem that if two breakpoints were set on consecutive addresses, the continue from the 
first breakpoint would skip the second.

llvm-svn: 166000

llvm-svn: 165999

llvm-svn: 165997

llvm-svn: 165995

llvm-svn: 165994

llvm-svn: 165993

llvm-svn: 165992

Added "process plugin packet send" and "process plugin packet history" for GDB remote. "process plugin packet send" will send a packet and receive a response. "process plugin packet history" will dump the packet history buffer.

llvm-svn: 165991

Clients can use the equivalent functions in MRI.

llvm-svn: 165990

- Besides used in SjLj exception handling, __builtin_setjmp/__longjmp is also
  used as a light-weight replacement of setjmp/longjmp which are used to
  implementation continuation, user-level threading, and etc. The support added
  in this patch ONLY addresses this usage and is NOT intended to support SjLj
  exception handling as zero-cost DWARF exception handling is used by default
  in X86.

llvm-svn: 165989

llvm-svn: 165988

 - This doesn't get used, but it is a simple workaround for PR14013.

llvm-svn: 165987

llvm-svn: 165986

All callers can simply use the corresponding MRI functions.

llvm-svn: 165985

Add range-based set()/reset() to BitVector.  These allow fast setting/resetting of ranges of bits, particularly useful when dealing with very large BitVector's.

llvm-svn: 165984

Using the cached bit vector in MRI avoids comstantly allocating and
recomputing the reserved register bit vector.

llvm-svn: 165983

Also provide an MRI::getReservedRegs() function to access the frozen
register set, and isReserved() and isAllocatable() methods to test
individual registers.

The various implementations of TRI::getReservedRegs() are quite
complicated, and many passes need to look at the reserved register set.
This patch makes it possible for these passes to use the cached copy in
MRI, avoiding a lot of malloc traffic and repeated calculations.

llvm-svn: 165982

rdar://12502028

llvm-svn: 165981

llvm-svn: 165980

lldb::BasicType
ClangASTContext::GetLLDBBasicTypeEnumeration (clang_type_t clang_type)

would return a bogus value.

llvm-svn: 165979

This fixes a CMake build break introduced by r165739.

Thanks Jan Voung for the quick suggestion/fix.

llvm-svn: 165978

llvm-svn: 165977