REX prefixes.

llvm-svn: 69108

This turns:

eq:
        %3 = icmp eq i32 %1, %2
        br label %join

ne:
        %4 = icmp ne i32 %1, %2
        br label %join

join:
        %5 = phi i1 [%3, %eq], [%4, %ne]
        br i1 %5, label %yes, label %no

=>

eq:
        %3 = icmp eq i32 %1, %2
        br i1 %3, label %yes, label %no

ne:
        %4 = icmp ne i32 %1, %2
        br i1 %4, label %yes, label %no

llvm-svn: 69102

any non-address uses of the address value. This fixes 186.crafty.

llvm-svn: 69094

llvm-svn: 69090

operator is used by a CopyToReg to export the value to a different
block, don't reuse the CopyToReg's register for the subreg operation
result if the register isn't precisely the right class for the
subreg operation.

Also, rename the h-registers.ll test, now that there are more
than one.

llvm-svn: 69087

Makes llvmc show error messages printed by child processes when run from the
Cygwin/MSYS shell. Since ExecuteAndWait does not return until the child program
has finished execution, this change should be harmless.

llvm-svn: 69082

llvm-svn: 69081

llvm-svn: 69049

llvm-svn: 69022

deleting, not just the basic block.

llvm-svn: 69011

memory and aren't volatile.  This was interfering with
good scheduling.

llvm-svn: 69008

Fix PR3934 part 2. findOnlyInterestingUse() was not setting IsCopy and IsDstPhys which are returned by value and used by callee. This happened to work on the earlier test cases because of a logic error in the caller side.

llvm-svn: 69006

llvm-svn: 68998

promoted to legal types without changing the type of the vector.  This is
following a suggestion from Duncan
(http://lists.cs.uiuc.edu/pipermail/llvmdev/2009-February/019923.html).
The transformation that used to be done during type legalization is now
postponed to DAG legalization.  This allows the BUILD_VECTORs to be optimized
and potentially handled specially by target-specific code.

It turns out that this is also consistent with an optimization done by the
DAG combiner: a BUILD_VECTOR and INSERT_VECTOR_ELT may be combined by
replacing one of the BUILD_VECTOR operands with the newly inserted element;
but INSERT_VECTOR_ELT allows its scalar operand to be larger than the
element type, with any extra high bits being implicitly truncated.  The
result is a BUILD_VECTOR where one of the operands has a type larger the
the vector element type.

Any code that operates on BUILD_VECTORs may now need to be aware of the
potential type discrepancy between the vector element type and the
BUILD_VECTOR operands.  This patch updates all of the places that I could
find to handle that case.

llvm-svn: 68996

it accordingly. Thanks to Jakob Stoklund Olesen for pointing
out how this might be useful.

llvm-svn: 68986

llvm-svn: 68981

llvm-svn: 68979

Right now, Debugging information to encode scopes (DW_TAG_lexical_block) relies on DBG_LABEL. Unfortunately this intefers with the quality of optimized code. 
This patch updates dwarf writer to encode scoping information in DWARF only in FastISel mode.

llvm-svn: 68973

Reapply 68847.
Now debug_inlined section is covered by TAI->doesDwarfUsesInlineInfoSection(), which is false by default.

llvm-svn: 68964

 - Add patterns for h-register extract, which avoids a shift and mask,
   and in some cases a temporary register.
 - Add address-mode matching for turning (X>>(8-n))&(255<<n), where
   n is a valid address-mode scale value, into an h-register extract
   and a scaled-offset address.
 - Replace X86's MOV32to32_ and related instructions with the new
   target-independent COPY_TO_SUBREG instruction.

On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.

These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.

llvm-svn: 68962

This will be used to replace things like X86's MOV32to32_.

Enhance ScheduleDAGSDNodesEmit to be more flexible and robust
in the presense of subregister superclasses and subclasses. It
can now cope with the definition of a virtual register being in
a subclass of a use.

Re-introduce the code for recording register superreg classes and
subreg classes. This is needed because when subreg extracts and
inserts get coalesced away, the virtual registers are left in
the correct subclass.

llvm-svn: 68961

ISD::SIGN_EXTEND_INREG. Tablegen-generated code can handle
these cases, and the scheduling issues observed earlier
appear to be resolved now.

llvm-svn: 68959

llvm-svn: 68958

a live interval. This is needed for some upcoming subreg changes.

llvm-svn: 68956

the subreg field to 0, since the subreg field is only used
for virtual register subregs. This doesn't change
current functionality; it just eliminates bogus noise from
debug output.

llvm-svn: 68955

llvm-svn: 68954

llvm-svn: 68953

llvm-svn: 68951

llvm-svn: 68950

This unbreaks the JIT on x86-64.

llvm-svn: 68948

llvm-svn: 68947

While passing arg of types larger than char only one byte at lower end was getting passed. We couldn't catch this as we did not have tests that were passing an int value larger than 256.

llvm-svn: 68946

declarations.

llvm-svn: 68944

to support C99 inline, GNU extern inline, etc.  Related bugzilla's
include PR3517, PR3100, & PR2933.  Nothing uses this yet, but it
appears to work.

llvm-svn: 68940

llvm-svn: 68939

interpreter mode" when it's not.

llvm-svn: 68937

patch by Alexei Svitkine!

llvm-svn: 68929

only if symbolic addresses are RIP relatives.

llvm-svn: 68924

llvm-svn: 68915

strncat :(

strncat(foo, "bar", 99)
would be optimized to
memcpy(foo+strlen(foo), "bar", 100, 1)
instead of
memcpy(foo+strlen(foo), "bar", 4, 1)"

Patch by Benjamin Kramer!

llvm-svn: 68905