REX prefixes.

llvm-svn: 69108

any non-address uses of the address value. This fixes 186.crafty.

llvm-svn: 69094

llvm-svn: 69049

llvm-svn: 69022

it accordingly. Thanks to Jakob Stoklund Olesen for pointing
out how this might be useful.

llvm-svn: 68986

Reapply 68847.
Now debug_inlined section is covered by TAI->doesDwarfUsesInlineInfoSection(), which is false by default.

llvm-svn: 68964

 - Add patterns for h-register extract, which avoids a shift and mask,
   and in some cases a temporary register.
 - Add address-mode matching for turning (X>>(8-n))&(255<<n), where
   n is a valid address-mode scale value, into an h-register extract
   and a scaled-offset address.
 - Replace X86's MOV32to32_ and related instructions with the new
   target-independent COPY_TO_SUBREG instruction.

On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.

These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.

llvm-svn: 68962

ISD::SIGN_EXTEND_INREG. Tablegen-generated code can handle
these cases, and the scheduling issues observed earlier
appear to be resolved now.

llvm-svn: 68959

llvm-svn: 68958

llvm-svn: 68954

llvm-svn: 68951

llvm-svn: 68950

This unbreaks the JIT on x86-64.

llvm-svn: 68948

llvm-svn: 68947

While passing arg of types larger than char only one byte at lower end was getting passed. We couldn't catch this as we did not have tests that were passing an int value larger than 256.

llvm-svn: 68946

to support C99 inline, GNU extern inline, etc.  Related bugzilla's
include PR3517, PR3100, & PR2933.  Nothing uses this yet, but it
appears to work.

llvm-svn: 68940

only if symbolic addresses are RIP relatives.

llvm-svn: 68924

llvm-svn: 68915

See comment for details.  This fixes rdar://6772169

llvm-svn: 68890

llvm-svn: 68887

hasImplicitDefOfPhysReg methods.  Use them to remove a 
look in X86 fast isel.

llvm-svn: 68886

from the assembler:

Error: unknown pseudo-op: `.debug_inlined'
llvm-svn: 68863

Keep track of inlined functions and their locations. This information is collected when nested llvm.dbg.func.start intrinsics are seen. (Right now, inliner removes nested llvm.dbg.func.start intrinisics during inlining.) 

Create debug_inlined dwarf section using these information. This info is used by gdb, at least on Darwin, to enable better experience debugging inlined functions. See DwarfWriter.cpp for more information on structure of debug_inlined section.

llvm-svn: 68847

llvm-svn: 68783

With this we generate

movl    %gs:0, %eax
leal    i@NTPOFF(%eax), %eax

instead of

movl    $i@NTPOFF, %eax
addl    %gs:0, %eax

llvm-svn: 68778

It turns out that there are still several problems with this, will file a bugzilla.

llvm-svn: 68749

llvm-svn: 68747

code that uses it by using SelectionDAG::getVTList instead.

llvm-svn: 68744

llvm-svn: 68730

register destinations that are tied to source operands.  The
TargetInstrDescr::findTiedToSrcOperand method silently fails for inline
assembly.  The existing MachineInstr::isRegReDefinedByTwoAddr was very
close to doing what is needed, so this revision makes a few changes to
that method and also renames it to isRegTiedToUseOperand (for consistency
with the very similar isRegTiedToDefOperand and because it handles both
two-address instructions and inline assembly with tied registers).

llvm-svn: 68714

The way we are trying to figure out banksel immediate operand may yield different results for different type of insns. This will eventually need to be changed but currently let us prevent the crash in cases of incorrect detection of banksel operand.

llvm-svn: 68713

Arguments to indirect calls were being passed incorrectly. They are not fixed to start after return value.

llvm-svn: 68705

llvm-svn: 68690

r68576 unconverd a bug in PIC16 port (Thanks to Dan Gohman) where we were custom lowering an ADD to ADDC.

llvm-svn: 68671

Convert TargetRegisterInfo's super-register checking to use a pre-computed hash table just like subregister checking does.

llvm-svn: 68669

llvm-svn: 68666

Tested by bootstrapping llvm-gcc and using that to build llvm.

llvm-svn: 68645

ARMTargetLowering::isLegalAddressingMode.

llvm-svn: 68619

llvm-svn: 68603

Emit .line debug directives for stoppoints. The debug location is retrieved by the MachineInstr itself, rather than by custom handling the DBG_STOPPOINT nodes.

llvm-svn: 68602