llvm-svn: 114931

llvm-svn: 114930

enable it for real. Leaving the CL option in place to it's easy to disable it
again if (when) testers find something I've missed.

llvm-svn: 114915

llvm-svn: 114896

enable it for real. Leaving the CL option in place to it's easy to disable it
again if (when) testers find something I've missed.

llvm-svn: 114892

llvm-svn: 114862

llc now recognizes the "intent" to support MC/obj emission for ARM, but
given that they are all stubs, it asserts on --filetype=obj --march=arm

Patch by Jason Kim.

llvm-svn: 114856

divide support also.

llvm-svn: 114813

llvm-svn: 114812

llvm-svn: 114784

llvm-svn: 114782

llvm-svn: 114780

llvm-svn: 114768

Fix scheduling itinerary for pseudo mov immediate instructions which expand into two real instructions.

llvm-svn: 114766

llvm-svn: 114758

llvm-svn: 114746

llvm-svn: 114723

reflection, this isn't going to achieve the purpose I intended it for.  Back to the drawing board!

llvm-svn: 114710

llvm-svn: 114709

llvm-svn: 114707

llvm-svn: 114706

llvm-svn: 114705

llvm-svn: 114703

llvm-svn: 114696

llvm-svn: 114689

Fix r114632. Return if the only terminator is an unconditional branch after the redundant ones are deleted.

llvm-svn: 114688

constant. Hopefully the non-Darwin bots will like it...

llvm-svn: 114687

llvm-svn: 114686

llvm-svn: 114684

(yet) recognize the 'trap' mnemonic, so we use .short/.long to emit the
opcode directly. On Darwin, however, we do want the mnemonic for more
readable assembly code and better disassembly.

Adjust the .td file to use the 'trap' mnemonic and handle using the binutils
workaround in the assembly printer. Also tweak the formatting of the opcode
values to make them consistent between the MC printer and the old printer.

llvm-svn: 114679

llvm-svn: 114676

but the first one. Those will never be executed. There was logic to do this
but it was faulty.

llvm-svn: 114632

new VariantKind to the MCSymbolExpr seems like overkill, but I'm not sure
there's a more straightforward way to get the printing difference captured.
(i.e., x86 uses @PLT, ARM uses (PLT)).

llvm-svn: 114613

llvm-svn: 114601

CombineTo to avoid putting the result on the worklist.  I don't think it makes
much difference for now, but it might help someday as we add more DAG
combine optimizations.

llvm-svn: 114595

of those.  Refactor to share code for handling BUILD_VECTOR(VMOVRRD).
I don't have a testcase that exercises this, but it seems like an obvious
good thing to do.

llvm-svn: 114589

llvm-svn: 114578

llvm-svn: 114576

llvm-svn: 114563

llvm-svn: 114555