llvm-svn: 188453

llvm-svn: 188452

llvm-svn: 188451

Summary:
There were several things going wrong:
- We mangled in useless qualifiers like "volatile void" return types.
- We didn't propagate 64-bit pointer markers sufficiently.
- We mangled qualifiers belonging to the pointee incorrectly.

This fixes PR16844 and PR16848.

Reviewers: rnk, whunt

Reviewed By: rnk

CC: cfe-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D1353

llvm-svn: 188450

Don't let isPermImmMask handle v16i32 since VPERMI doesn't match on that type. Remove 128-bit vector handling from isPermImmMask too, it's covered by isPSHUFDMask.

llvm-svn: 188449

llvm-svn: 188448

llvm-svn: 188447

llvm-svn: 188446

llvm-svn: 188445

We were marking both LLVMBUILDOUTPUT and LLVMBUILDERRORS as
ERROR_VARIABLES when clearly LLVMBUILDOUTPUT should be marked as
OUTPUT_VARIABLE.

llvm-svn: 188444

where the executable has been slid.  This detects the regression fixed in
r188289.

llvm-svn: 188443

llvm-svn: 188442

Replace getValueType().getSimpleVT() with getSimpleValueType(). Also remove one weird cast from MVT->EVT just to call getSimpleVT().

llvm-svn: 188441

Also use the more common "derive from" in place of "extend" in another
comment.

llvm-svn: 188440

llvm-svn: 188439

properties (direct or indirect) setter/getter (or declared 
methods as well) are seen by the method implementation type 
matching logic before declaration of method in super class 
is seen. This fixes the warning coming out of that method mismatch.
// rdar://14650159

llvm-svn: 188438

When new virtual registers are created during splitting/spilling, defer
creation of the live interval until we need to use the live interval.

Along with the recent commits to notify LiveRangeEdit when new virtual
registers are created, this makes it possible for functions like
TargetInstrInfo::loadRegFromStackSlot() and
TargetInstrInfo::storeRegToStackSlot() to create multiple virtual
registers as part of the process of generating loads/stores for
different register classes, and then have the live intervals for those
new registers computed when they are needed.

llvm-svn: 188437

MachineInstrSpan is initialized with a MachineBasicBlock::iterator,
and is intended to track which instructions are inserted before/after
that instruction from the time the MachineInstrSpan is created.

It provides a begin()/end() interface to walk the range of
instructions inserted around the initial instruction (including that
initial instruction).

It also provides a getInitial() interface to return the initial
iterator.

llvm-svn: 188436

Add a delegate class to MachineRegisterInfo with a single virtual
function, MRI_NoteNewVirtualRegister(). Update LiveRangeEdit to inherit
from this delegate class and override the definition of the callback
with an implementation that tracks the newly created virtual registers.

llvm-svn: 188435

Track new virtual registers by register number, rather than by the live
interval created for them. This is the first step in separating the
creation of new virtual registers and new live intervals.  Eventually
live intervals will be created and populated on demand after the virtual
registers have been created and used in instructions.

llvm-svn: 188434

This is intended to be a simplified API, whose internals are
deliberately less efficient for the purpose of a simplified interface,
for use with clients that want to query the analyzer's heuristics for
determining retain count semantics.

There are no immediate clients, but it is intended to be used
by the ObjC modernizer.

llvm-svn: 188433

This is a WIP change to allow other clients to query the retain count
heuristics of the static analyzer.

llvm-svn: 188432

This should fix hangs in the OpenCL piglit tests.

llvm-svn: 188431

llvm-svn: 188430

Now that compute support is better on SI, we can't continue using v16i8
for descriptors since this is also a legal type in OpenCL.

This patch fixes numerous hangs with the piglit OpenCL test and since
we now use a target specific DAG node for LOAD_CONSTANT with the
correct MemOperandFlags, this should also fix:

https://bugs.freedesktop.org/show_bug.cgi?id=66805

llvm-svn: 188429

We switched from i32 to i8 types a while ago and the tests were never
updated.

llvm-svn: 188428

Using REG_SEQUENCE for BUILD_VECTOR rather than a series of INSERT_SUBREG
instructions should make it easier for the register allocator to coalasce
unnecessary copies.

v2:
  - Use an SGPR register class if all the operands of BUILD_VECTOR are
    SGPRs.

llvm-svn: 188427

The instruction selector will now try to infer the destination register
so it can decided whether to use V_MOV_B32 or S_MOV_B32 when copying
immediates.

llvm-svn: 188426

The previous code declared the operand as unknown:$vaddr, which made
it possible for scalar registers to be used instead of vector registers.

llvm-svn: 188425

llvm-svn: 188424

llvm-svn: 188423

DebugInfo: Prefer references over pointers, pass by const reference for a type that will grow in the future

llvm-svn: 188422

Patch by: Marek Olšák

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
llvm-svn: 188421

Patch by: Marek Olšák

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
llvm-svn: 188420

Patch by: Marek Olšák

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
llvm-svn: 188419

This fixes the F2U opcode for the Mesa driver.

Patch by: Marek Olšák

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
llvm-svn: 188418

llvm-svn: 188417

 - This cleans up the text output of failing tests when run under PY3.

llvm-svn: 188416

llvm-svn: 188415

llvm-svn: 188414