Separate AVXCC and SSECC printing for cmpps/pd/ss/sd and add masking before the switch statement. This keeps the unreachable default case from being hit if the instruction was created with an intrinsic with too large of an immediate.

llvm-svn: 165483

Remove some unused code in the X86AsmPrinter. Add LLVM_OVERRIDE and virtual keywords to the remaining interface methods.

llvm-svn: 165478

llvm-svn: 165418

llvm-svn: 165402

Otherwise it will try to use SSE patterns and fail horribly if sse is disabled.
Fixes PR14035.

llvm-svn: 165377

llvm-svn: 165324

llvm-svn: 165303

Move expansion of SETB_C(8/16/32/64)r from MCInstLower to ExpandPostRAPseudos and mark them as pseudos in the td file.

llvm-svn: 165302

Follow up to r165072. Try a different approach: only move the load when it's going to be folded into the call. rdar://12437604

llvm-svn: 165287

segmented registers.  Test case to come.

llvm-svn: 165275

a pointer to a type, in order to remove the uses of getGlobalContext().

Patch by Tyler Nowicki.

llvm-svn: 165255

a) frame setup instructions define the prologue
b) we shouldn't change our location mid-stream

Add a test to make sure that the stack adjustment stays within
the prologue.

llvm-svn: 165250

- Add 'HwEncoding' for X86 registers and call getEncodingValue() to
  retrieve their encoding values.
- This's the first step to adopt new scheme. Furthur revising is onging.

llvm-svn: 165241

llvm-svn: 165205

llvm-svn: 165182

in the Intel syntax.

The MC layer supports emitting in the Intel syntax, but this would require the
inline assembly MachineInstr to be lowered to an MCInst before emission.  This
is potential future work, but for now emitting directly from the MachineInstr
suffices.

llvm-svn: 165173

llvm-svn: 165141

enums. This allows for better encapsulation of the Attributes class.

llvm-svn: 165132

Corrects a problem whereby MCSchedModel was not being set up when
the CPU type was auto-detected.

Patch by Andy Zhang.

llvm-svn: 165122

more detail.

llvm-svn: 165099

llvm-svn: 165089

Enable the pass by default for targets that request it, and change the
-enable-early-ifcvt to the opposite -disable-early-ifcvt.

There are still some x86 regressions when enabling early if-conversion
because of the missing machine models. Disable the pass for x86 until
machine models are added.

llvm-svn: 165075

X86DAGToDAGISel::PreprocessISelDAG(), isel is moving load inside
callseq_start / callseq_end so it can be folded into a call. This can
create a cycle in the DAG when the call is glued to a copytoreg. We
have been lucky this hasn't caused too many issues because the pre-ra
scheduler has special handling of call sequences. However, it has
caused a crash in a specific tailcall case.

rdar://12393897

llvm-svn: 165072

This reverts 165055 and 165052 temporarily while I look at debugger
failures.

llvm-svn: 165071

llvm-svn: 165069

llvm-svn: 165063

of operand is specific to MS-style inline assembly and should not be generated
when parsing normal assembly.

The purpose of the wildcard operands are to allow the AsmParser to match
multiple instructions (i.e., MCInsts) to a given ms-style asm statement.  For
the time being the matcher just returns the first match.  This patch only
implements wildcard matches for memory operands.  Support for register
wildcards will be added in the near future.

llvm-svn: 165057

prologue. Also skip frame setup instructions when looking for the
first location.

llvm-svn: 165052

llvm-svn: 165051

in the block.

llvm-svn: 165050

with just an insert point from the MachineBasicBlock and let
the location be updated as we access it.

llvm-svn: 165049

This adds 'elf' as a recognized target triple environment value and overrides the default generated object format on Windows platforms if that value is present.  This patch also enables MCJIT tests on Windows using the new environment value.

llvm-svn: 165030

map constraints and MCInst operands to inline asm operands.  This replaces the
getMCInstOperandNum() function.

The logic to determine the constraints are not in place, so we still default to
a register constraint (i.e., "r"). Also, we no longer build the MCInst but
rather return just the opcode to get the MCInstrDesc.

llvm-svn: 164979

llvm-svn: 164926

Change getX86SubSuperRegister to take an MVT::SimpleValueType rather than an EVT and add llvm_unreachable to the switches. Helps it compile to dramatically better code.

llvm-svn: 164919

second output of SUB with first output of TEST.

PR13966

llvm-svn: 164835

Revert 'Fix a typo 'iff' => 'if''. iff is an abreviation of if and only if. See: http://en.wikipedia.org/wiki/If_and_only_if Commit 164767

llvm-svn: 164768

llvm-svn: 164767

The hasFnAttr method has been replaced by querying the Attributes explicitly. No
intended functionality change.

llvm-svn: 164725

If the offset is more than 24-bits, it won't fit in a scattered
relocation offset field, so we fall back to using a non-scattered
relocation.

rdar://12358909

llvm-svn: 164724