- Jan 15, 2013
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Jack Carter authored
we need to generate a N64 compound relocation R_MIPS_GPREL_32/R_MIPS_64/R_MIPS_NONE. The bug was exposed by the SingleSourcetest case DuffsDevice.c. Contributer: Jack Carter llvm-svn: 172496
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- Jan 08, 2013
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Jack Carter authored
an R_MIPS_GPREL16 relocation. Contributer: Jack Carter llvm-svn: 171882
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Jack Carter authored
value in the 64 bit .eh_frame section. It doesn't however allow exception handling to work yet since it depends on the correct relocation model being set in the ELF header flags. Contributer: Jack Carter llvm-svn: 171881
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Eli Bendersky authored
No change in functionality. llvm-svn: 171822
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- Dec 16, 2012
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Reed Kotler authored
Mips16 is really a processor decoding mode (ala thumb 1) and in the same program, mips16 and mips32 functions can exist and can call each other. If a jal type instruction encounters an address with the lower bit set, then the processor switches to mips16 mode (if it is not already in it). If the lower bit is not set, then it switches to mips32 mode. The linker knows which functions are mips16 and which are mips32. When relocation is performed on code labels, this lower order bit is set if the code label is a mips16 code label. In general this works just fine, however when creating exception handling tables and dwarf, there are cases where you don't want this lower order bit added in. This has been traditionally distinguished in gas assembly source by using a different syntax for the label. lab1: ; this will cause the lower order bit to be added lab2=. ; this will not cause the lower order bit to be added In some cases, it does not matter because in dwarf and debug tables the difference of two labels is used and in that case the lower order bits subtract each other out. To fix this, I have added to mcstreamer the notion of a debuglabel. The default is for label and debug label to be the same. So calling EmitLabel and EmitDebugLabel produce the same result. For various reasons, there is only one set of labels that needs to be modified for the mips exceptions to work. These are the "$eh_func_beginXXX" labels. Mips overrides the debug label suffix from ":" to "=." . This initial patch fixes exceptions. More changes most likely will be needed to DwarfCFException to make all of this work for actual debugging. These changes will be to emit debug labels in some places where a simple label is emitted now. Some historical discussion on this from gcc can be found at: http://gcc.gnu.org/ml/gcc-patches/2008-08/msg00623.html http://gcc.gnu.org/ml/gcc-patches/2008-11/msg01273.html llvm-svn: 170279
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- Dec 10, 2012
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Akira Hatanaka authored
getMipsRegisterNumbering and use MCRegisterInfo::getEncodingValue instead. llvm-svn: 169760
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- Dec 03, 2012
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Chandler Carruth authored
Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
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- Nov 22, 2012
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Jack Carter authored
This patch provides support for the MIPS relocations: *) R_MIPS_GOT_HI16 *) R_MIPS_GOT_LO16 *) R_MIPS_CALL_HI16 *) R_MIPS_CALL_LO16 These are used for large GOT instruction sequences. Contributer: Jack Carter llvm-svn: 168471
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- Nov 21, 2012
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Akira Hatanaka authored
llvm-svn: 168450
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- Oct 03, 2012
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Jack Carter authored
for the number of bytes in a particular instruction to using const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode()); Desc.getSize() This is necessary with the advent of 16 bit instructions with mips16 and micromips. It is also puts Mips in compliance with the other targets for getting instruction size. llvm-svn: 165171
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Jack Carter authored
The mips 64bit instructions DSLL, DSRA, DSRL, DEXT and DINS get transformed by the assembler or through codegen direct object output to other variants based on the value of the immediate values of the operands. If the code is generated as assembler, this transformation does not occur assuming that it will occur later in the assembler. This code was originally called from MipsAsmPrinter.cpp and we needed to check for OutStreamer.hasRawTextSupport(). This was not a good place for it and has been moved to MCTargetDesc/MipsMCCodeEmitter.cpp where both direct object and the assembler use it it automagically. The test cases have been checked in for a number of weeks now. llvm-svn: 165067
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- Sep 26, 2012
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Akira Hatanaka authored
getMipsRegisterNumbering. llvm-svn: 164720
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- Sep 18, 2012
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Roman Divacky authored
store this and use it to not emit long nops when the CPU is geode which doesnt support them. Fixes PR11212. llvm-svn: 164132
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- Sep 15, 2012
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Craig Topper authored
llvm-svn: 163973
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- Sep 14, 2012
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Dmitri Gribenko authored
* wrap code blocks in \code ... \endcode; * refer to parameter names in paragraphs correctly (\arg is not what most people want -- it starts a new paragraph); * use \param instead of \arg to document parameters in order to be consistent with the rest of the codebase. llvm-svn: 163902
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- Sep 12, 2012
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Dmitri Gribenko authored
llvm-svn: 163721
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- Sep 07, 2012
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Jack Carter authored
Test cases included Contributer: Vladimir Medic llvm-svn: 163363
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- Sep 06, 2012
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Jack Carter authored
Test case included. Contributer: Vladimir Medic llvm-svn: 163277
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- Aug 22, 2012
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Jack Carter authored
within the codegen EK_GPRel64BlockAddress. This was not supported for direct object output and resulted in an assertion. This change adds support for EK_GPRel64BlockAddress for direct object. One fallout from this is to turn on rela relocations for mips64 to match gas. llvm-svn: 162334
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- Aug 17, 2012
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Akira Hatanaka authored
No new tests are added. All tests in ExecutionEngine/MCJIT that have been failing pass after this patch is applied (when "make check" is done on a mips board). Patch by Petar Jovanovic. llvm-svn: 162135
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- Aug 07, 2012
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Jack Carter authored
I hit this in a very large program (spirit.cpp), but have not figured out how to make a small make check test for it. llvm-svn: 161366
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- Aug 06, 2012
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Jack Carter authored
These 2 relocations gain access to the highest and the second highest 16 bits of a 64 bit object. R_MIPS_HIGHER %higher(A+S) The %higher(x) function is [ (((long long) x + 0x80008000LL) >> 32) & 0xffff ]. R_MIPS_HIGHEST %highest(A+S) The %highest(x) function is [ (((long long) x + 0x800080008000LL) >> 48) & 0xffff ]. llvm-svn: 161348
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- Jul 23, 2012
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Akira Hatanaka authored
llvm-svn: 160636
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- Jul 21, 2012
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Akira Hatanaka authored
llvm-svn: 160599
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- Jul 13, 2012
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Jack Carter authored
is used in cases where global symbols are directly represented in the GOT and we use an offset into the global offset table. This patch adds direct object support for R_MIPS_GOT_DISP. llvm-svn: 160183
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- Jul 12, 2012
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Jack Carter authored
When WriteFragmentData() case FT_align called Asm.getBackend().writeNopData() is called, nothing is done since Mips implementation of writeNopData just returned "true". For some reason this has not caused problems in 32 bit mode, but in 64 bit mode it caused an assert when processing multiple function units. The test case included will assert without this patch. It runs twice with different flags to prevent false positives due to changes in code generation over time. llvm-svn: 160084
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- Jul 02, 2012
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Jack Carter authored
Contributer: Sasa Stankovic llvm-svn: 159574
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- Jun 28, 2012
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Jack Carter authored
It takes advantage of r159299 which introduces relocation support for N64. elf-dump needed to be upgraded to support N64 relocations as well. This passes make check. Jack llvm-svn: 159301
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Jack Carter authored
which many Mips 64 ABIs use than for O64 which many if not all other target ABIs use. Most architectures have the following 64 bit relocation record format: typedef struct { Elf64_Addr r_offset; /* Address of reference */ Elf64_Xword r_info; /* Symbol index and type of relocation */ } Elf64_Rel; typedef struct { Elf64_Addr r_offset; Elf64_Xword r_info; Elf64_Sxword r_addend; } Elf64_Rela; Whereas N64 has the following format: typedef struct { Elf64_Addr r_offset;/* Address of reference */ Elf64_Word r_sym; /* Symbol index */ Elf64_Byte r_ssym; /* Special symbol */ Elf64_Byte r_type3; /* Relocation type */ Elf64_Byte r_type2; /* Relocation type */ Elf64_Byte r_type; /* Relocation type */ } Elf64_Rel; typedef struct { Elf64_Addr r_offset;/* Address of reference */ Elf64_Word r_sym; /* Symbol index */ Elf64_Byte r_ssym; /* Special symbol */ Elf64_Byte r_type3; /* Relocation type */ Elf64_Byte r_type2; /* Relocation type */ Elf64_Byte r_type; /* Relocation type */ Elf64_Sxword r_addend; } Elf64_Rela; The structure is the same size, but the r_info data element is now 5 separate elements. Besides the content aspects, endian byte reordering will be different for the area with each element being endianized separately. I treat this as generic and continue to pass r_type as an integer masking and unmasking the byte sized N64 values for N64 mode. I've implemented this and it causes no affect on other current targets. This passes make check. Jack llvm-svn: 159299
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- Jun 14, 2012
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Akira Hatanaka authored
llvm-svn: 158471
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- Jun 09, 2012
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Jack Carter authored
llvm-svn: 158250
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- May 15, 2012
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Jim Grosbach authored
Add the MCRegisterInfo to the factories and constructors. Patch by Tom Stellard <Tom.Stellard@amd.com>. llvm-svn: 156828
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- Apr 22, 2012
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Bill Wendling authored
llvm-svn: 155307
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- Apr 17, 2012
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Akira Hatanaka authored
Patch by Vladimir Medic. llvm-svn: 154935
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- Apr 16, 2012
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Akira Hatanaka authored
llvm-svn: 154838
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- Apr 03, 2012
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Akira Hatanaka authored
llvm-svn: 153925
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Akira Hatanaka authored
Patch by Vladimir Medic. llvm-svn: 153924
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- Apr 02, 2012
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Akira Hatanaka authored
This patch allows llvm to recognize that a 64 bit object file is being produced and that the subsequently generated ELF header has the correct information. The test case checks for both big and little endian flavors. Patch by Jack Carter. llvm-svn: 153889
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Craig Topper authored
Make MCInstrInfo available to the MCInstPrinter. This will be used to remove getInstructionName and the static data it contains since the same tables are already in MCInstrInfo. llvm-svn: 153860
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- Mar 31, 2012
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Akira Hatanaka authored
llvm-svn: 153795
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