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  1. Jan 15, 2013
    • Jack Carter's avatar
      This patch fixes a Mips specific bug where · f238510c
      Jack Carter authored
      we need to generate a N64 compound relocation
      R_MIPS_GPREL_32/R_MIPS_64/R_MIPS_NONE.
      
      The bug was exposed by the SingleSourcetest case 
      DuffsDevice.c.
      
      Contributer: Jack Carter
      llvm-svn: 172496
      f238510c
  2. Jan 08, 2013
  3. Dec 16, 2012
    • Reed Kotler's avatar
      This patch is needed to make c++ exceptions work for mips16. · aee4d5d1
      Reed Kotler authored
      Mips16 is really a processor decoding mode (ala thumb 1) and in the same
      program, mips16 and mips32 functions can exist and can call each other.
      
      If a jal type instruction encounters an address with the lower bit set, then
      the processor switches to mips16 mode (if it is not already in it). If the
      lower bit is not set, then it switches to mips32 mode.
      
      The linker knows which functions are mips16 and which are mips32.
      When relocation is performed on code labels, this lower order bit is
      set if the code label is a mips16 code label.
      
      In general this works just fine, however when creating exception handling
      tables and dwarf, there are cases where you don't want this lower order
      bit added in.
      
      This has been traditionally distinguished in gas assembly source by using a
      different syntax for the label.
      
      lab1:      ; this will cause the lower order bit to be added
      lab2=.     ; this will not cause the lower order bit to be added
      
      In some cases, it does not matter because in dwarf and debug tables
      the difference of two labels is used and in that case the lower order
      bits subtract each other out.
      
      To fix this, I have added to mcstreamer the notion of a debuglabel.
      The default is for label and debug label to be the same. So calling
      EmitLabel and EmitDebugLabel produce the same result.
      
      For various reasons, there is only one set of labels that needs to be
      modified for the mips exceptions to work. These are the "$eh_func_beginXXX" 
      labels.
      
      Mips overrides the debug label suffix from ":" to "=." .
      
      This initial patch fixes exceptions. More changes most likely
      will be needed to DwarfCFException to make all of this work
      for actual debugging. These changes will be to emit debug labels in some
      places where a simple label is emitted now.
      
      Some historical discussion on this from gcc can be found at:
      http://gcc.gnu.org/ml/gcc-patches/2008-08/msg00623.html
      http://gcc.gnu.org/ml/gcc-patches/2008-11/msg01273.html 
      
      llvm-svn: 170279
      aee4d5d1
  4. Dec 10, 2012
  5. Dec 03, 2012
    • Chandler Carruth's avatar
      Use the new script to sort the includes of every file under lib. · ed0881b2
      Chandler Carruth authored
      Sooooo many of these had incorrect or strange main module includes.
      I have manually inspected all of these, and fixed the main module
      include to be the nearest plausible thing I could find. If you own or
      care about any of these source files, I encourage you to take some time
      and check that these edits were sensible. I can't have broken anything
      (I strictly added headers, and reordered them, never removed), but they
      may not be the headers you'd really like to identify as containing the
      API being implemented.
      
      Many forward declarations and missing includes were added to a header
      files to allow them to parse cleanly when included first. The main
      module rule does in fact have its merits. =]
      
      llvm-svn: 169131
      ed0881b2
  6. Nov 22, 2012
    • Jack Carter's avatar
      Mips direct object xgot support · b05cb67b
      Jack Carter authored
      This patch provides support for the MIPS relocations:
      
          *)  R_MIPS_GOT_HI16
          *)  R_MIPS_GOT_LO16
          *)  R_MIPS_CALL_HI16
          *)  R_MIPS_CALL_LO16
      
      These are used for large GOT instruction sequences.
      
      Contributer: Jack Carter
      llvm-svn: 168471
      b05cb67b
  7. Nov 21, 2012
  8. Oct 03, 2012
    • Jack Carter's avatar
      This patch moves from using a hard coded number (4) · 5b5559d3
      Jack Carter authored
      for the number of bytes in a particular instruction
      to using
         const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode());
         Desc.getSize()
      
      This is necessary with the advent of 16 bit instructions with
      mips16 and micromips. It is also puts Mips in compliance with
      the other targets for getting instruction size.
      
      llvm-svn: 165171
      5b5559d3
    • Jack Carter's avatar
      The mips 64bit instructions DSLL, DSRA, DSRL, DEXT and DINS get transformed by... · aa7aeaa0
      Jack Carter authored
      The mips 64bit instructions DSLL, DSRA, DSRL, DEXT and DINS get transformed by the assembler or through codegen direct object output to other variants based on the value of the immediate values of the operands.
      
      If the code is generated as assembler, this transformation does not occur assuming that it will occur later in the assembler.
      
      This code was originally called from  MipsAsmPrinter.cpp and we needed to check for OutStreamer.hasRawTextSupport(). This was not a good place for it and has been moved to MCTargetDesc/MipsMCCodeEmitter.cpp where both direct object and the assembler use it it automagically.
      
      The test cases have been checked in for a number of weeks now.
      
      llvm-svn: 165067
      aa7aeaa0
  9. Sep 26, 2012
  10. Sep 18, 2012
  11. Sep 15, 2012
  12. Sep 14, 2012
    • Dmitri Gribenko's avatar
      Fix Doxygen issues: · 5485acd4
      Dmitri Gribenko authored
      * wrap code blocks in \code ... \endcode;
      * refer to parameter names in paragraphs correctly (\arg is not what most
        people want -- it starts a new paragraph);
      * use \param instead of \arg to document parameters in order to be consistent
        with the rest of the codebase.
      
      llvm-svn: 163902
      5485acd4
  13. Sep 12, 2012
  14. Sep 07, 2012
  15. Sep 06, 2012
  16. Aug 22, 2012
    • Jack Carter's avatar
      For mips64 switch statements in subroutines could generate · 77064c05
      Jack Carter authored
      within the codegen EK_GPRel64BlockAddress. This was not 
      supported for direct object output and resulted in an assertion.
      
      This change adds support for EK_GPRel64BlockAddress for 
      direct object.
      
      One fallout from this is to turn on rela relocations 
      for mips64 to match gas.
      
      llvm-svn: 162334
      77064c05
  17. Aug 17, 2012
  18. Aug 07, 2012
  19. Aug 06, 2012
    • Jack Carter's avatar
      Mips relocations R_MIPS_HIGHER and R_MIPS_HIGHEST. · 84491abb
      Jack Carter authored
      These 2 relocations gain access to the 
      highest and the second highest 16 bits
      of a 64 bit object.
      
      R_MIPS_HIGHER %higher(A+S)
      The %higher(x) function is [ (((long long) x + 0x80008000LL) >> 32) & 0xffff ]. 
      
      R_MIPS_HIGHEST %highest(A+S)
      The %highest(x) function is [ (((long long) x + 0x800080008000LL) >> 48) & 0xffff ]. 
      
      llvm-svn: 161348
      84491abb
  20. Jul 23, 2012
  21. Jul 21, 2012
  22. Jul 13, 2012
    • Jack Carter's avatar
      The Mips specific relocation R_MIPS_GOT_DISP · 5ddcfda8
      Jack Carter authored
      is used in cases where global symbols are 
      directly represented in the GOT and we use an 
      offset into the global offset table.
      
      This patch adds direct object support for R_MIPS_GOT_DISP.
      
      llvm-svn: 160183
      5ddcfda8
  23. Jul 12, 2012
    • Jack Carter's avatar
      Patch for Mips direct object generation. · 570ae0b1
      Jack Carter authored
      When WriteFragmentData() case FT_align called
      Asm.getBackend().writeNopData() is called, nothing
      is done since Mips implementation of writeNopData just
      returned "true".
      
      For some reason this has not caused problems in 32 bit
      mode, but in 64 bit mode it caused an assert when processing
      multiple function units.
      
      The test case included will assert without this patch. It
      runs twice with different flags to prevent false positives
      due to changes in code generation over time.
      
      llvm-svn: 160084
      570ae0b1
  24. Jul 02, 2012
  25. Jun 28, 2012
    • Jack Carter's avatar
      This allows hello world to be compiled for Mips 64 direct object. · b9f9de93
      Jack Carter authored
      It takes advantage of r159299 which introduces relocation support for N64. 
      elf-dump needed to be upgraded to support N64 relocations as well.
      
      This passes make check.
      
      Jack
      
      llvm-svn: 159301
      b9f9de93
    • Jack Carter's avatar
      The ELF relocation record format is different for N64 · 8ad0c272
      Jack Carter authored
      which many Mips 64 ABIs use than for O64 which many 
      if not all other target ABIs use.
      
      Most architectures have the following 64 bit relocation record format:
      
        typedef struct
        {
          Elf64_Addr   r_offset; /* Address of reference */
          Elf64_Xword  r_info;   /* Symbol index and type of relocation */
        } Elf64_Rel;
      
        typedef struct
        {
          Elf64_Addr    r_offset;
          Elf64_Xword   r_info;
          Elf64_Sxword  r_addend;
        } Elf64_Rela;
      
      Whereas N64 has the following format:
      
        typedef struct
        {
          Elf64_Addr    r_offset;/* Address of reference */
          Elf64_Word  r_sym;     /* Symbol index */
          Elf64_Byte  r_ssym;    /* Special symbol */
          Elf64_Byte  r_type3;   /* Relocation type */
          Elf64_Byte  r_type2;   /* Relocation type */
          Elf64_Byte  r_type;    /* Relocation type */
        } Elf64_Rel;
      
        typedef struct
        {
          Elf64_Addr    r_offset;/* Address of reference */
          Elf64_Word  r_sym;     /* Symbol index */
          Elf64_Byte  r_ssym;    /* Special symbol */
          Elf64_Byte  r_type3;   /* Relocation type */
          Elf64_Byte  r_type2;   /* Relocation type */
          Elf64_Byte  r_type;    /* Relocation type */
          Elf64_Sxword  r_addend;
        } Elf64_Rela;
      
      The structure is the same size, but the r_info data element 
      is now 5 separate elements. Besides the content aspects, 
      endian byte reordering will be different for the area with 
      each element being endianized separately.
      
      I treat this as generic and continue to pass r_type as 
      an integer masking and unmasking the byte sized N64 
      values for N64 mode. I've implemented this and it causes no 
      affect on other current targets.
      
      This passes make check.
      
      Jack
      
      llvm-svn: 159299
      8ad0c272
  26. Jun 14, 2012
  27. Jun 09, 2012
  28. May 15, 2012
  29. Apr 22, 2012
  30. Apr 17, 2012
  31. Apr 16, 2012
  32. Apr 03, 2012
  33. Apr 02, 2012
  34. Mar 31, 2012
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