Add HasAVX1Only predicate and use it for patterns that have an AVX1 instruction and an AVX2 instruction rather than relying on AddedComplexity.

llvm-svn: 162654

Reviewed offline by chandlerc.

llvm-svn: 162623

llvm-svn: 162622

ARMConstantIslandPass expects this instruction to stay in the same basic
block as the jump table branch.

llvm-svn: 162615

It's not clear that they should be marked as such, but tbb formation
fails if t2LEApcrelJT is hoisted of of a loop.

This doesn't change the flags on these instructions,
UnmodeledSideEffects was already inferred from the missing pattern.

llvm-svn: 162603

The ARM BL and BLX instructions don't have predicate operands, but the
thumb variants tBL and tBLX do.

The argument registers should be added as implicit uses.

llvm-svn: 162593

There is special magic happening when returning floating point values on
the x87 stack. The RET instructions get extra f80 operands.

llvm-svn: 162592

It is legal to have a register node as an explicit operand, it shouldn't
be counted as an implicit use.

llvm-svn: 162591

llvm-svn: 162589

second operand is MipsISD::GPRel.

llvm-svn: 162584

the case of multiple edges from one block to another.

A simple example is a switch statement with multiple values to the same
destination. The definition of an edge is modified from a pair of blocks to
a pair of PredBlock and an index into the successors.

Also set the weight correctly when building SelectionDAG from LLVM IR,
especially when converting a Switch.
IntegersSubsetMapping is updated to calculate the weight for each cluster.

llvm-svn: 162572

[asan/tsan] rename FunctionBlackList* to BlackList* as this class is not limited to functions any more

llvm-svn: 162566

[asan/tsan] extend the functionality of FunctionBlackList to globals and modules. Patch by Reid Watson. 

llvm-svn: 162565

In collaboration with Adhemerval Zanella.

llvm-svn: 162562

No intended behavior change.  This was introduced in r162023.  With the fixed
algorithm a Release build of ARMInstPrinter.cpp goes from 16s to 10s on a
2011 MBP.

llvm-svn: 162559

llvm-svn: 162558

llvm-svn: 162557

llvm-svn: 162556

llvm-svn: 162534

not in darwin gdb compat mode.

Fixes rdar://10975088

llvm-svn: 162526

TODO: Fix code duplication and coding style.
llvm-svn: 162525

llvm-svn: 162524

llvm-svn: 162520

llvm-svn: 162518

They were inserted to silence TableGen's warning about
redundant properties. That warning is now gone.

llvm-svn: 162517

llvm-svn: 162515

llvm-svn: 162514

Fix undefined behavior (signed integer overflow) when Clang parses a hexfloat with an enormous exponent. Caught by an existing unit test + -ftrapv.

llvm-svn: 162505

llvm-svn: 162499

llvm-svn: 162498

output (we're emitting a specification already and the information
isn't changing) and we're not in old gdb compat mode.

Saves 1% on the debug information for a build of llvm.

Fixes rdar://11043421

llvm-svn: 162493

turned on and off separate from the platform if you're on darwin.

llvm-svn: 162487

we're using the darwin old gdb compat mode for emitting dwarf.

llvm-svn: 162486

No test case, this is a generalization of r160260.

llvm-svn: 162485

Keep track of the set/unset state of these bits along with their
true/false values, but treat '?' as '0' for now.

llvm-svn: 162461

llvm-svn: 162454

llvm-svn: 162446

llvm-svn: 162438

with older gdbs on darwin.

rdar://10975874

llvm-svn: 162436

rdar://10393214

llvm-svn: 162434