-feature flag, instructions definitions, test cases

llvm-svn: 175196

The important fix is that the constant interpolation value is stored in the
parameter slot P0, which is encoded as 2.

In addition, drop the SI_INTERP_CONST pseudo instruction, pass the parameter
slot as an operand to V_INTERP_MOV_F32 instead of hardcoding it there, and
add a special operand class for the parameter slots for type checking and
pretty printing.

NOTE: This is a candidate for the Mesa stable branch.

Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 175193

llvm-svn: 175189

This patch doesn't introduce any functionality changes.

llvm-svn: 175187

inline asm with 64-bit data on ARM

Update test case to use -mtriple=arm-linux-gnueabi

llvm-svn: 175186

It fixes around 100 tfb piglit tests and 16 glean tests.

NOTE: This is a candidate for the Mesa stable branch.

Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
llvm-svn: 175183

This allows MachineInstScheduler to reorder them, and thus make scheduling more
efficient.

Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
llvm-svn: 175182

Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
llvm-svn: 175181

This fixes a couple of regressions on (probably not just) cayman

NOTE: This is a candidate for the Mesa stable branch.

Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
llvm-svn: 175180

llvm-svn: 175176

If vector types have legal register classes, then LLVM bypasses LegalizeTypes
on them, which causes faults currently since the code to handle them isn't in
place.

This fixes test failures when AArch64 is the default target.

llvm-svn: 175172

Only comments affected. No code change at all.

llvm-svn: 175169

The parser will now accept instructions with alignment specifiers written like
    vld1.8  {d16}, [r0:64]
, while also still accepting the incorrect syntax
    vld1.8  {d16}, [r0, :64]

llvm-svn: 175164

Added a test.

llvm-svn: 175144

Fixes assertion failure in newly added lit test. Might just be a bandaid that
needs to be revisited.

llvm-svn: 175139

llvm-svn: 175133

up so that we can apply the direct object emitter patch. This patch
should be a nop right now and it's test is to not break what is already
there.
 

llvm-svn: 175126

llvm-svn: 175121

Since functions with internal linkage don't have language linkage, it is valid
to overload them:

extern "C" {
       static int foo();
       static int foo(int);
}

So we mangle them.

llvm-svn: 175120

llvm-svn: 175107

llvm-svn: 175102

NOTE: This is a candidate for the Mesa stable branch.
llvm-svn: 175096

Fixes PR15250!

llvm-svn: 175092

llvm-svn: 175088

instead of redefining separate instructions for them.

llvm-svn: 175086

displacements.
rdar://12974533

llvm-svn: 175083

if the offset fits in 11 bits. This makes use of the fact that the abi
requires sp to be 8 byte aligned so the actual offset can fit in 8
bits. It will be shifted left and sign extended before being actually used.
The assembler or direct object emitter will shift right the 11 bit
signed field by 3 bits. We don't need to deal with that here.

llvm-svn: 175073

llvm-svn: 175067

via -print-after-all.

llvm-svn: 175058

This happens when there is both stack realignment and a dynamic alloca in the
function. If we overwrite %esi (rep;movsl uses fixed registers) we'll lose the
base pointer and the next register spill will write into oblivion.

Fixes PR15249 and unbreaks firefox on i386/freebsd. Mozilla uses dynamic allocas
and freebsd a 4 byte stack alignment.

llvm-svn: 175057

llvm-svn: 175044

Prevent insertion of "vzeroupper" before call that preserves YMM registers, since a caller uses preserved registers across the call.

llvm-svn: 175043

assembly.

llvm-svn: 175036

llvm-svn: 175020

instructions.

llvm-svn: 174973

Vectors were being manually scalarized by the backend.  Instead,
let the target-independent code do all of the work.  The manual
scalarization was from a time before good target-independent support
for scalarization in LLVM. However, this forces us to specially-handle
vector loads and stores, which we can turn into PTX instructions that
produce/consume multiple operands.

llvm-svn: 174968

'R600/SI: Use proper instructions for array/shadow samplers.' removed two
cases from TEX_SHADOW. Vincent Lejeune reported on IRC that this broke some
shadow array piglit tests with the r600g driver. Reinstating the removed
cases should fix this, and still works with radeonsi as well.

I will follow up with some lit tests which would have caught the regression.

NOTE: This is a candidate for the Mesa stable branch.

Tested-by: Vincent Lejeune <vljn@ovi.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 174963

A reverse shuffle is lowered to a vrev and possibly a vext instruction (quad
word).

radar://13171406

llvm-svn: 174933

Lower reverse shuffles to a vrev64 and a vext instruction instead of the default
legalization of storing and loading to the stack. This is important because we
generate reverse shuffles in the loop vectorizer when we reverse store to an
array.

  uint8_t Arr[N];
  for (i = 0; i < N; ++i)
    Arr[N - i - 1] = ...

radar://13171760

llvm-svn: 174929

Fixed decode of existing 3dNow prefetchw instruction
Intel is scheduled to add a compatible prefetchw (same encoding) to future CPUs

llvm-svn: 174920