- Incorporate Chris' comment suggestion.

llvm-svn: 51061

llvm-svn: 51060

llvm-svn: 51057

- Correct a pasto.

llvm-svn: 51054

A brief description about PIC16:
===============================
PIC16 is an 8-bit microcontroller with only one 8-bit register which is the 
accumulator. All arithmetic/load/store operations are 8-bit only.
The architecture has two address spaces: program and data. The program memory 
is divided into 2K pages and the data memory is divided into banks of 128 byte, with only 80 usable bytes, resulting in an non-contiguous data memory. 

It supports direct data memory access (by specifying the address as part of the instruction) and indirect data and program memory access (in an unorthodox fashion which utilize a 16 bit pointer register). 

Two classes of registers exist: (8-bit class which is only one
accumulator) (16-bit class, which contains one or more 16 bit
pointer(s))

llvm-svn: 51027

Instead of a vector load, shuffle and then extract an element. Load the element from address with an offset.
        pshufd $1, (%rdi), %xmm0
        movd %xmm0, %eax
=>
        movl 4(%rdi), %eax

llvm-svn: 51026

llvm-svn: 51020

llvm-svn: 51019

several things that were neither in an anonymous namespace nor static
but not intended to be global.

llvm-svn: 51017

Teach X86 a few more vsetcc patterns.  Custom lowering for unsupported ones is next.

llvm-svn: 51009

Xform bitconvert(build_pair(load a, load b)) to a single load if the load locations are at the right offset from each other.

llvm-svn: 51008

"is{Trivially,Really}ReMaterializable" methods.

llvm-svn: 51001

llvm-svn: 51000

encoding information.

llvm-svn: 50997

llvm-svn: 50991

This is necessary to unbreak the build.

llvm-svn: 50988

in a non-void function that calls abort.

llvm-svn: 50969

llvm-svn: 50959

llvm-svn: 50940

than silently generate invalid code.

llvm-gcc does not currently use VAArgInst; it lowers va_arg in the
front-end.

llvm-svn: 50930

llvm-svn: 50929

llvm-svn: 50928

llvm-svn: 50922

Note, some of the code will be moved into target independent part of DAG combiner in a subsequent patch.

llvm-svn: 50918

llvm-svn: 50874

Handle vector move / load which zero the destination register top bits (i.e. movd, movq, movss (addr), movsd (addr)) with X86 specific dag combine.

llvm-svn: 50838

on x86-64 linux.  This causes no regressions on
32 bit linux and 32 bit ppc.  More tests pass
on 64 bit ppc with no regressions.  I didn't
turn on eh on 64 bit linux because the intrinsics
needed to compile the eh runtime aren't done
yet.  But if you turn it on and link with the
mainline runtime then eh seems to work fine
on x86-64 linux with this patch.  Thanks to
Dale for testing.  The main point of the patch
is that if you output that some object is
encoded using 4 bytes you had better not output
8 bytes for it: the patch makes everything
consistent.

llvm-svn: 50825

llvm-svn: 50698

llvm-svn: 50696

llvm-svn: 50681

llvm-svn: 50677

llvm-svn: 50675

llvm-svn: 50663

llvm-svn: 50660

llvm-svn: 50654

llvm-svn: 50649

the code being generated does not require an executable stack.

Also, add target-specific code to make use of this on Linux
on x86. 

llvm-svn: 50634

but should work. Work is in progress, more models will follow

llvm-svn: 50630

Select vector shift with non-immediate i32 shift amount operand by first moving the operand into the right register.

llvm-svn: 50619

Add separate intrinsics for MMX / SSE shifts with i32 integer operands. This allow us to simplify the horribly complicated matching code.

llvm-svn: 50601