code in other segments) to the Intel instruction
tables.

llvm-svn: 81953

llvm-svn: 81923

Intel tables, where the source operand is
specified by the R/M field and the destination
operand by the Reg field.

llvm-svn: 81914

to the Intel register table.
Added 16- and 64-bit MOVs to and from the segment
registers to the Intel instruction tables.

llvm-svn: 81895

versions of CALL and JMP with segmented addresses
provided in-line, as pairs of immediates.

llvm-svn: 81818

for the purposes of the disassembler.

llvm-svn: 81603

operand widths to the Intel instruction tables, for
the purposes of the disassembler.

llvm-svn: 81601

64-bit variants for the disassembler.

llvm-svn: 81591

on rAX and an immediate.

llvm-svn: 81551

various widths.

llvm-svn: 81458

including segment offsets and (for 8-bit operands)
absolute offsets.

llvm-svn: 81457

ones capable of accessing R/M operands instead of just
registers.

llvm-svn: 81456

disabling the use of 16-bit operations on x86. This doesn't yet work for
inline asms with 16-bit constraints, vectors with 16-bit elements,
trampoline code, and perhaps other obscurities, but it's enough to try
some experiments.

llvm-svn: 80930

instruction tables to support segmented addressing (and other objects
of obscure type).
Modified the X86 assembly printers to handle these new operand types.
Added JMP and CALL instructions that use segmented addresses.

llvm-svn: 80857

Added a 64-bit ADD %RAX, imm32 instruction.
Added all 4 forms for AND %rAX, imm and CMP %rAX, imm.

llvm-svn: 80746

Added TEST %rAX, $imm instructions to the Intel tables.  These are required for the X86 disassembler.

llvm-svn: 80696

a register to 0. This fixes PR4814.

llvm-svn: 80445

llvm-svn: 80271

llvm-svn: 80232

moves. This avoids the need to promote the operands (or implicitly
extend them, a partial register update condition), and can reduce
i8 register pressure. This substantially speeds up code such as
write_hex in lib/Support/raw_ostream.cpp.

subclass-coalesce.ll is too trivial and no longer tests what it was
originally intended to test.

llvm-svn: 80184

leads to partial-register definitions. To help avoid redundant
zero-extensions, also teach the h-register matching patterns that
use movzbl to match anyext as well as zext.

llvm-svn: 80099

the register save area if %al is 0. This avoids touching xmm
regsiters when they aren't actually used.

llvm-svn: 79061

llvm-svn: 78733

 - Used to mark fake instructions which don't correspond to an actual machine
   instruction (or are duplicates of a real instruction). This is to be used for
   "special cases" in the .td files, which should be ignored by things like the
   assembler and disassembler. We still need a good solution to handle pervasive
   duplication, like with the Int_ instructions.

 - Set the bit on fake "mov 0" style instructions, which allows turning an
   assembler matcher warning into a hard error.

 - -2 FIXMEs.

llvm-svn: 78731

tables.

llvm-svn: 78721

llvm-svn: 78680

INT i8.  These instructions are only for interpretation by disassemblers, not
for emission, so they do not as yet have patterns.

llvm-svn: 78630

llvm-svn: 78587

structure.

llvm-svn: 78581

 - We can now discriminate SUB32ri8 from SUB32ri, for example.

llvm-svn: 78530

 -2 FIXMEs.

llvm-svn: 78523

llvm-svn: 78299

llvm-svn: 78293

PR4572. A few tests have some minor code regressions due to different
coalescing.

llvm-svn: 78217

Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.

This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.

This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.

llvm-svn: 78142

Unbreak Win64 CC. Step one: honour register save area, fix some alignment and provide a different set of call-clobberred registers.

llvm-svn: 77962

llvm-svn: 77894

llvm-svn: 77893

Optimize some common usage patterns of atomic built-ins __sync_add_and_fetch() and __sync_sub_and_fetch. 

When the return value is not used (i.e. only care about the value in the memory), x86 does not have to use add to implement these. Instead, it can use add, sub, inc, dec instructions with the "lock" prefix.

This is currently implemented using a bit of instruction selection trick. The issue is the target independent pattern produces one output and a chain and we want to map it into one that just output a chain. The current trick is to select it into a merge_values with the first definition being an implicit_def. The proper solution is to add new ISD opcodes for the no-output variant. DAG combiner can then transform the node before it gets to target node selection.

Problem #2 is we are adding a whole bunch of x86 atomic instructions when in fact these instructions are identical to the non-lock versions. We need a way to add target specific information to target nodes and have this information carried over to machine instructions. Asm printer (or JIT) can use this information to add the "lock" prefix.

llvm-svn: 77582

due to x86 encoding restrictions. This is currently off by default
because it may cause code quality regressions. This is for PR4572.

llvm-svn: 77565