llvm-svn: 121196

llvm-svn: 121167

an assert, at least.

llvm-svn: 121166

CodeGenInstruction into its own helper class.  No functionality change.

llvm-svn: 117893

ARM instructions with:

foo GPR, rGPR

which happens a lot.

llvm-svn: 112025

llvm-svn: 111996

and optional def operands are handled in the backend support.

llvm-svn: 111220

llvm-svn: 109572

llvm-svn: 109407

llvm-svn: 109043

llvm-svn: 108071

 - Check getBytesToPopOnReturn().
 - Eschew ST0 and ST1 for return values.
 - Fix the PIC base register initialization so that it doesn't ever
   fail to end up the top of the entry block.

llvm-svn: 108039

U    utils/TableGen/FastISelEmitter.cpp
--- Reverse-merging r107943 into '.':
U    test/CodeGen/X86/fast-isel.ll
U    test/CodeGen/X86/fast-isel-loads.ll
U    include/llvm/Target/TargetLowering.h
U    include/llvm/Support/PassNameParser.h
U    include/llvm/CodeGen/FunctionLoweringInfo.h
U    include/llvm/CodeGen/CallingConvLower.h
U    include/llvm/CodeGen/FastISel.h
U    include/llvm/CodeGen/SelectionDAGISel.h
U    lib/CodeGen/LLVMTargetMachine.cpp
U    lib/CodeGen/CallingConvLower.cpp
U    lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
U    lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
U    lib/CodeGen/SelectionDAG/FastISel.cpp
U    lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
U    lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
U    lib/CodeGen/SelectionDAG/InstrEmitter.cpp
U    lib/CodeGen/SelectionDAG/TargetLowering.cpp
U    lib/Target/XCore/XCoreISelLowering.cpp
U    lib/Target/XCore/XCoreISelLowering.h
U    lib/Target/X86/X86ISelLowering.cpp
U    lib/Target/X86/X86FastISel.cpp
U    lib/Target/X86/X86ISelLowering.h

llvm-svn: 107987

llvm-svn: 107947

Debug info intrinsics win for now.

llvm-svn: 107850

around everywhere, and also give it an InsertPt member, to enable isel
to operate at an arbitrary position within a block, rather than just
appending to a block.

llvm-svn: 107791

llvm-svn: 104845

This is the beginning of purely symbolic subregister indices, but we need a bit
of jiggling before the explicit numeric indices can be completely removed.

llvm-svn: 104492

llvm-svn: 103529

doesn't have to guess.

llvm-svn: 103194

in some more places.

llvm-svn: 99366

to maintain a list of types (one for each result of
the node) instead of a single type.  There are liberal
hacks added to emulate the old behavior in various
situations, but they can start disolving now.

llvm-svn: 98999

llvm-svn: 98904

changing the primary datastructure from being a 
"std::vector<unsigned char>" to being a new TypeSet class
that actually has (gasp) invariants!

This changes more things than I remember, but one major
innovation here is that it enforces that named input 
values agree in type with their output values.

This also eliminates code that transparently assumes (in 
some cases) that SDNodeXForm input/output types are the
same, because this is wrong in many case.

This also eliminates a bug which caused a lot of ambiguous
patterns to go undetected, where a register class would
sometimes pick the first possible type, causing an
ambiguous pattern to get arbitrary results.

With all the recent target changes, this causes no 
functionality change!

llvm-svn: 98534

uses several kinds of opcode values which are not declared within
that enum. This fixes PR5946.

llvm-svn: 92794

icc (#177, partial).  Patch by Erick Tryzelaar.

llvm-svn: 81106

the latter is capable of representing either a primitive or an extended type.

llvm-svn: 78713

llvm-svn: 78610

 - Sorry, I can't help myself.

 - No intended functionality change.

llvm-svn: 74742

operand is the last in a pattern.  There is no
reason this should be true (although apparently
it always is right now).

llvm-svn: 72232

Eliminate a couple of fields from TargetRegisterClass: SubRegClasses and SuperRegClasses. These are not necessary. Also eliminate getSubRegisterRegClass and getSuperRegisterRegClass. These are slow and their results can change if register file names change. Just use TargetLowering::getRegClassFor() to get the right TargetRegisterClass instead.

llvm-svn: 62762

This will allow predicates to be composed, which will allow the
predicate definitions to become less redundant, and eventually
will allow DAGISelEmitter.cpp to emit less redundant code.

llvm-svn: 57562

they'll be a little more visible. Also, update and reword them a bit.

llvm-svn: 56877

Correctly handle physical register inputs. They are not explicit input operands in the resulting machine instrs.

llvm-svn: 55893

llvm-svn: 55876

def : Pat<(i8 (trunc GR32:$src)),
          (i8 (EXTRACT_SUBREG (MOV32to32_ GR32:$src), x86_subreg_8bit))>

llvm-svn: 55875

Let tblgen only generate fastisel routines, not the class definition. This makes it easier for targets to define its own fastisel class.

llvm-svn: 55679

llvm-svn: 55545

llvm-svn: 55512

Add support for fast-isel of opcodes that require use of extract_subreg.  Because of how extract_subreg is treated, it requires special case handling.

llvm-svn: 55480