llvm-svn: 104118

template names. We were completely missing naming classes for many unqualified
lookups, but this didn't trigger code paths that need it. This removes part of
an optimization that re-uses the template name lookup done by the parser to
determine if explicit template arguments actually form a template-id.
Unfortunately the technique for avoiding the duplicate lookup lost needed data
such as the class context in which the lookup succeeded.

llvm-svn: 104117

CALL64pcrel32, for the same reason.

llvm-svn: 104116

t2LEApcrel and tLEApcrel are re-materializable. This makes it possible to hoist more loads during machine LICM.

llvm-svn: 104115

llvm-svn: 104114

llvm-svn: 104113

llvm-svn: 104112

Mark pattern-less mayLoad / mayStore instructions neverHasSideEffects. These do not have other un-modeled side effects.

llvm-svn: 104111

llvm-svn: 104110

avoid same prefix byte problem as in r104062.

llvm-svn: 104108

way regardless of whether some overloaded operator functions were
found by name lookup within the template. Fixes PR6851.

llvm-svn: 104107

llvm-svn: 104106

llvm-svn: 104105

the same .cpp file as provided the definitions referenced these functions,
hiding the issue. However, they are clearly no longer inline. Let me know if
there is a reason to move their definitions to the header and make them truly
inline.

llvm-svn: 104104

llvm-svn: 104103

Mark a few more pattern-less instructions with neverHasSideEffects. This is especially important on instructions like t2LEApcreal which are prime candidate for machine LICM.

llvm-svn: 104102

welcome for one.

llvm-svn: 104101

llvm-svn: 104095

Intrinsics which do a vector compare (results are all zero or all ones) are modeled as icmp / fcmp + sext. This is turned into a vsetcc by dag combine (yes, not a good long term solution). The targets can then isel the vsetcc to the appropriate instruction.

The trouble arises when the result of a vector cmp + sext is then and'ed with all ones. Instcombine will turn it into a vector cmp + zext, dag combiner will miss turning it into a vsetcc and hell breaks loose after that.

Teach dag combine to turn a vector cpm + zest into a vsetcc + and 1. This fixes rdar://7923010.

llvm-svn: 104094

opcodes into a helper function. This fixes a few places in the code
which were not properly selecting the 8-bit-immediate opcodes.

llvm-svn: 104091

llvm-svn: 104090

llvm-svn: 104089

constants in registers which partially cancel out their immediate fields.

llvm-svn: 104088

of its formulae have been removed into a helper function, and also
teach it how to update the RegUseTracker.

llvm-svn: 104087

in the coalescer's instruction map.

llvm-svn: 104086

llvm-svn: 104085

gc attributes to be inline with Objective-C
(for radar 7925141).

llvm-svn: 104084

expressions in attributes, pragmas.

llvm-svn: 104083

function.

llvm-svn: 104082

involves extending implicit conversion sequences to model vector
conversions and vector splats, along with teaching the C++ conditional
operator-checking code about vector types.

Fixes <rdar://problem/7983501>.

llvm-svn: 104081

llvm-svn: 104080

a helper function.

llvm-svn: 104079

llvm-svn: 104078

is inconsistent with the BaseRegs field. It's not print's job to
assert on an invalid condition, but it can make one more obvious.

llvm-svn: 104077

confusion with LSRInstance's RegUses member.

llvm-svn: 104076

forward declarations and definitions of structs/classes/enums.

llvm-svn: 104075

llvm-svn: 104074

llvm-svn: 104073

llvm-svn: 104068

specified.

llvm-svn: 104066