Commits · 10ab29ec6eaf3ee0a70574b4cb6f79a4df01d47d · Roger Ferrer / llvm-epi · GitLab

Nov 14, 2022
- [IRCE] Bail out if AddRec in icmp is for another loop (PR58912) · 10ab29ec
  Dmitry Makogon authored Nov 11, 2022
  10ab29ec
- [RISCV] Add PACKH/PACKW/PACK to hasAllNBitUsers. · 3b759798
  Craig Topper authored Nov 13, 2022
  
  3b759798
- [RISCV] Add another PACKH pattern. · 3ac93d1f
  Craig Topper authored Nov 13, 2022
  3ac93d1f
- [Support] Use std::is_scalar_v (NFC) · d709888b
  Kazu Hirata authored Nov 13, 2022
  
  d709888b
- Add missing include. · c9845735
  Johannes Reifferscheid authored Nov 14, 2022
  
  c9845735
- [Docs] Add Documentation on BOLT Build Configs · b9378a60
  Aiden Grossman authored Nov 14, 2022
  b9378a60
- [Docs] Add Documentation on (Thin)LTO + PGO Build Configs · f7dea680
  Aiden Grossman authored Nov 12, 2022
  f7dea680
- [lldb] Re-phase comments in `ScriptedThread.get_stackframes` method (NFC) · e85c7233
  Med Ismail Bennani authored Nov 13, 2022
  e85c7233
- [lldb] Remove unused `stack_memory_dump` member from ScriptedProcess class (NFC) · 1239d37b
  Med Ismail Bennani authored Nov 13, 2022
  1239d37b
- [RISCV] Improve PACKH instruction selection · 40ae4b89
  Craig Topper authored Nov 13, 2022
  40ae4b89
- [RISCV] Don't use zero-stride vector load if there's no optimized u-arch · c66b6977
  Pengcheng Wang authored Nov 14, 2022
  c66b6977
- [C++20] [Modules] Emit Macro Definition in -module-file-info action · 360c5fe5
  Chuanqi Xu authored Nov 11, 2022
  360c5fe5
- Apply clang-tidy fixes for readability-identifier-naming in MergerTest.cpp (NFC) · f7f917a7
  Mehdi Amini authored Nov 03, 2022
  
  f7f917a7
- Apply clang-tidy fixes for llvm-qualified-auto in AttrOrTypeFormatGen.cpp (NFC) · 2e9cd81d
  Mehdi Amini authored Nov 03, 2022
  
  2e9cd81d
- Apply clang-tidy fixes for llvm-qualified-auto in MLIRContext.cpp (NFC) · 375e5e95
  Mehdi Amini authored Nov 03, 2022
  
  375e5e95
- [RISCV] Add PACKW and PACKH to isSignExtendingOpW in RISCVSExtWRemoval. · 1f258887
  Craig Topper authored Nov 13, 2022
  1f258887
- [RISCV] Improve selection of PACKW. · 1a8ba9e1
  Craig Topper authored Nov 13, 2022
  1a8ba9e1
- [LoopFlatten] Forget all block and loop dispositions after flatten · 98eb9179
  luxufan authored Nov 11, 2022
  98eb9179
- [LoongArch] Expand atomicrmw fadd/fsub/fmin/fmax with CmpXChg · 19ae5391
  gonglingqin authored Nov 14, 2022
  19ae5391
- [RISCV][NFC] Remove dead code. · 0c0681b7
  Yeting Kuo authored Nov 13, 2022
  0c0681b7
- [RISCV] Fix incorrect early out from isSignExtendedW in RISCVSExtWRemoval. · 03f9009c
  Craig Topper authored Nov 13, 2022
  03f9009c
- [RISCV] Add test for incorrect sext.w removal. NFC · fe0d4ba3
  Craig Topper authored Nov 13, 2022
  
  fe0d4ba3
- [PowerPC] Use ArrayRef (NFC) · 16d969ca
  Kazu Hirata authored Nov 13, 2022
  16d969ca
- [RISCV] Improve selection of PACK/PACKW for AssertZExt input. · 95388f73
  Craig Topper authored Nov 13, 2022
  
  95388f73
Nov 13, 2022
- [IR] Use llvm::any_of (NFC) · 378778a0
  Kazu Hirata authored Nov 13, 2022
  
  378778a0
- [Hexagon] Use `Register` instead of `unsigned`, NFC · c0abd057
  Krzysztof Parzyszek authored Nov 13, 2022
  c0abd057
- [lldb][test] Avoid UB in optimized_code test · 99a05667
  Arthur Eubanks authored Nov 13, 2022
  
  99a05667
- [VectorUtils] Skip interleave members with diff type and alloca sizes. · 758699c3
  Florian Hahn authored Nov 13, 2022
  758699c3
- [clang][test] Avoid UB in overload.cl · e564f515
  Arthur Eubanks authored Nov 13, 2022
  
  e564f515
- [Hexagon] Pass Hexagon::PC to InitializeHexagonMCRegisterInfo · 1a6d7704
  Krzysztof Parzyszek authored Nov 13, 2022
  1a6d7704
- [Hexagon] Remove unneeded HexagonRegisterInfo::getRARegister · 110825b6
  Krzysztof Parzyszek authored Nov 13, 2022
  110825b6
- [Hexagon] Reduce the spill alignment for double/quad vector classes · 475d2289
  Krzysztof Parzyszek authored Nov 13, 2022
  475d2289
- [RISCV] Add BREV8 to hasAllWUsers in RISCVSExtWRemoval. · 6373f8c3
  Craig Topper authored Nov 13, 2022
  6373f8c3
- [RISCV] Add PACK/PACKH/PACKW to hasAllWUsers in RISCVSExtWRemoval. · 9e14ffa4
  Craig Topper authored Nov 13, 2022
  
  9e14ffa4
- [MLIR] Move JitRunner Options to header, pass to mlirTransformer · 1b99e8ba
  Renato Golin authored Nov 12, 2022
  1b99e8ba
- Move variable declarations out of #if guard, NFC · 6b9a79f9
  Krzysztof Parzyszek authored Nov 12, 2022
  6b9a79f9
- [SimpleLoopUnswitch] Forget SCEVs for replaced phis. · 7854a1ab
  Florian Hahn authored Nov 13, 2022
  7854a1ab
- [MLIR][Bytecode] Ensure `dataIt` is aligned coming out of `EncodingReader::alignTo`. · ae461d8b
  bzcheeseman authored Nov 11, 2022
  ae461d8b
- [X86] Regenerate combine-movmsk.ll · d9bff270
  Simon Pilgrim authored Nov 13, 2022
  d9bff270
- Revert "[InstCombine] allow more folds for multi-use selects (2nd try)" · 362c2350
  Sanjay Patel authored Nov 13, 2022
  362c2350