Commits · 182a65adcf8af922246cac80ea6f3fdb159cd89e · Roger Ferrer / llvm-epi · GitLab

Oct 16, 2023
- [RISCV] Refactor performCONCAT_VECTORSCombine. NFC (#69068) · 182a65ad
  Luke Lau authored Oct 16, 2023
  182a65ad
- [RISCV] Use f64 for LocVT for ilp32 when whole f64 is passed on the stack. NFC (#69118) · 58c9ef5a
  Craig Topper authored Oct 15, 2023
  58c9ef5a
- [RISCV][GISel] Don't setType on PtrReg in RISCVInstructionSelector::replacePtrWithInt. · e3f53320
  Craig Topper authored Oct 15, 2023
  e3f53320
- [RISCV][NFC] Remove space · 019d67f1
  Pengcheng Wang authored Oct 12, 2023
  
  019d67f1
Oct 14, 2023
- [RISCV] Add CompressPat for c.beqz/bnez with X0 in the first operand. (#69042) · 66203762
  Craig Topper authored Oct 14, 2023
  
  66203762
- [RISCV] Move hasOneUse() call after opcode check. · 51438184
  Craig Topper authored Oct 13, 2023
  51438184
- [RISCV][GISel] Legalize G_SMULO/G_UMULO (#67635) · 3750558e
  Craig Topper authored Oct 13, 2023
  3750558e
Oct 13, 2023
- [RISCV][GISel] Add isel patterns for ADDIW/SRLIW/SRAIW/SLLIW and remove custom selection. (#68470) · 9d1a3fdd
  Craig Topper authored Oct 13, 2023
  9d1a3fdd
- Use llvm::endianness::{big,little,native} (NFC) · 4a0ccfa8
  Kazu Hirata authored Oct 12, 2023
  4a0ccfa8
Oct 11, 2023
- [RISCV] Add Stackmap/Statepoint/Patchpoint support without targets · 776889bc
  Sacha Coppey authored Oct 11, 2023
  776889bc
- [RISCV] Make PostRAScheduler a target feature (#68692) · f3c92a06
  Pengcheng Wang authored Oct 11, 2023
  f3c92a06
- Revert "[RISCV] Shrink vslideup's LMUL when lowering fixed insert_subvector (#65997)" · 3a6cc52f
  Philip Reames authored Oct 10, 2023
  3a6cc52f
Oct 10, 2023
- [RISCV][GlobalISel] Select G_PTR_ADD (#67605) · 45a29bd5
  Nitin John Raj authored Oct 10, 2023
  45a29bd5
- [RISCV][GlobalISel] Select G_ICMP, G_LOAD, G_STORE, G_ZEXTLOAD (#67619) · 86d6b379
  Nitin John Raj authored Oct 10, 2023
  86d6b379
- [RISCV][GlobalISel] Lower calls to variadic functions (#68271) · 9bb71226
  Nitin John Raj authored Oct 10, 2023
  9bb71226
- [RISCV][NFC] Correct/clarify RISCVPushPopOptimizer.cpp header comment · fc654b4f
  Alex Bradbury authored Oct 10, 2023
  fc654b4f
- [RISCV][NFC] Correct RISCVInstrInfoZc.td header comment - Zc* extensions no longer experimental · 0c8c9e83
  Alex Bradbury authored Oct 10, 2023
  0c8c9e83
- [RISCV][NFC] Remove mention of experimental extensions from RISCVInstrInfoZb.td header · 23b9418b
  Alex Bradbury authored Oct 10, 2023
  23b9418b
- [RISCV] Simplify PatSetCC_m and PatFprFprDynFrm_m (#68562) · 7645df6b
  Shao-Ce SUN authored Oct 10, 2023
  7645df6b
Oct 09, 2023
- [RISCV] Generaize reduction tree matching to fp sum reductions (#68599) · 08b20d83
  Philip Reames authored Oct 09, 2023
  08b20d83
Oct 08, 2023
- [RISCV][NFC] Add base classes of Operand and uimm/simm (#68472) · 18622fc2
  Pengcheng Wang authored Oct 08, 2023
  18622fc2
- [RISCV] Support fptoi like ops for fp16 vectors input when only have Zvfhmin (#67532) · 76fc8715
  Jianjian GUAN authored Oct 08, 2023
  76fc8715
Oct 07, 2023
- [RISCV] Add sink-and-fold support for RISC-V. (#67602) · 45636ecf
  Craig Topper authored Oct 07, 2023
  45636ecf
- [RISCV][GISel] Add FPR register bank. · ee9f96bd
  Craig Topper authored Oct 06, 2023
  ee9f96bd
Oct 06, 2023
- [RISCV][GISel] Select G_SELECT (#67614) · 7f9a50ff
  Nitin John Raj authored Oct 06, 2023
  7f9a50ff
- [RISCV] Support VLS for VCIX (#67289) · 70368eae
  Brandon Wu authored Oct 07, 2023
  
  70368eae
- [RISCV] Strip W suffix from ADDIW (#68425) · 86240751
  Philip Reames authored Oct 06, 2023
  86240751
Oct 05, 2023
- [RISCV] Use early return to simplify isFPImmLegal [nfc] · 3aa2bac6
  Philip Reames authored Oct 05, 2023
  3aa2bac6
- [IR]Add NumSrcElts param to is..Mask static function in ShuffleVectorInst. · e22818d5
  Alexey Bataev authored Aug 21, 2023
  e22818d5
Oct 04, 2023
- Revert "[IR]Add NumSrcElts param to is..Mask static function in ShuffleVectorInst." · 07389535
  Arthur Eubanks authored Oct 04, 2023
  07389535
- [RISCV] Fix illegal build_vector when lowering double id buildvec on RV32 (#67017) · 3b0b84fd
  Luke Lau authored Oct 04, 2023
  3b0b84fd
- [RISCV][GlobalISel] Legalize G_FRAME_INDEX (#67746) · da9f9082
  Nitin John Raj authored Oct 04, 2023
  da9f9082
- [RISCV] Relax vslide*_vl patterns to allow any mask. NFC (#68203) · 982639fd
  Luke Lau authored Oct 04, 2023
  982639fd
- [RISCV][ISel] Fix comment to match direction of predicate in code. NFC. (#68248) · 92da28aa
  Michael Maitland authored Oct 04, 2023
  92da28aa
- [RISCV] Generaize reduction tree matching to all integer reductions (#68014) (reapply) · 45a334d3
  Philip Reames authored Oct 04, 2023
  45a334d3
- [RISCV] Don't try to form VECREDUCE without vector instructions · 199cbec9
  Philip Reames authored Oct 04, 2023
  199cbec9
- [IR]Add NumSrcElts param to is..Mask static function in ShuffleVectorInst. · b186f1f6
  Alexey Bataev authored Aug 21, 2023
  b186f1f6
- Revert "[RISCV] Generaize reduction tree matching to all integer reductions (#68014)" · 824251c9
  Alex Bradbury authored Oct 04, 2023
  824251c9
Oct 03, 2023
- Revert "[IR]Add NumSrcElts param to is..Mask static function in ShuffleVectorInst." · 1129dec7
  Alexey Bataev authored Oct 03, 2023
  1129dec7
- [IR]Add NumSrcElts param to is..Mask static function in ShuffleVectorInst. · 6f43d28f
  Alexey Bataev authored Aug 21, 2023
  6f43d28f