Commits · 182a65adcf8af922246cac80ea6f3fdb159cd89e · Roger Ferrer / llvm-epi · GitLab

Aug 19, 2023
- [RISCV] Rename Ventana DecoderNamespace to XVentana for matching other extension. NFC. · f3c0eaeb
  Jim Lin authored Aug 19, 2023
  f3c0eaeb
Jul 30, 2023
- [RISCV] Rename XTHead DecoderNamespaces to match their extension names include the 'X'. NFC · b4bb111b
  Craig Topper authored Jul 30, 2023
  b4bb111b
- [RISCV] Rename DecoderNamespace for XCVsimd to be consistent with other XCV extensions. NFC · 0c7d8976
  Craig Topper authored Jul 30, 2023
  
  0c7d8976
Jul 28, 2023
- [RISCV] Add support for XCVbi extension in CV32E40P · afb9c04a
  melonedo authored Jul 28, 2023
  afb9c04a
- Revert "[RISCV] Add support for XCVbi extension in CV32E40P" · e4777dc4
  melonedo authored Jul 28, 2023
  e4777dc4
- [RISCV] Add support for XCVbi extension in CV32E40P · bf2ad26b
  melonedo authored Jun 25, 2023
  bf2ad26b
- [RISCV] Add support for XCVsimd extension in CV32E40P · 3c0604b2
  melonedo authored Jun 11, 2023
  3c0604b2
- [RISCV] Add support for XCValu extension in CV32E40P · 092e60a3
  Qihan Cai authored Jul 20, 2023
  092e60a3
Jun 26, 2023
- [RISCV] Add support for custom instructions for Sifive S76. · 4c37d30e
  Garvit Gupta authored Jun 26, 2023
  4c37d30e
Jun 21, 2023
- [RISCV] Add support for XCVmac extension in CV32E40P · e219dd88
  Qihan Cai authored Jun 21, 2023
  e219dd88
Jun 19, 2023
- [RISCV] Add support for XCVbitmanip extension in CV32E40P · c5a412da
  melonedo authored Jun 14, 2023
  c5a412da
May 25, 2023
- [RISCV][NFC] Simplify decoding code of disassembler · 92723d5a
  Pengcheng Wang authored May 25, 2023
  92723d5a
May 16, 2023
- [RISCV] Rework how implied SP operands work in the disassembler. NFC · 8f43c3f4
  Craig Topper authored May 16, 2023
  8f43c3f4
May 08, 2023
- [RISCV] Add MC support of RISCV zcmp Extension · 6b55e911
  WuXinlong authored May 08, 2023
  6b55e911
May 05, 2023
- [RISCV] Add DecoderNamespace to Zcmt instructions. · 7b3b178c
  Craig Topper authored May 05, 2023
  7b3b178c
- [RISCV] Directly create MCOperands from addImplySP in Disassembler. NFC · d421c5f8
  Craig Topper authored May 04, 2023
  d421c5f8
Apr 10, 2023
- [RISCV] Support assembler and dis-assembler for VCIX extension. · 0b9a620b
  Nelson Chu authored Apr 14, 2022
  0b9a620b
Mar 27, 2023
- [RISCV] Replace RISCV -> RISC-V in comments. NFC · 29463612
  Craig Topper authored Mar 27, 2023
  29463612
Mar 23, 2023
- [RISCV][MC] Add support for RV64E · c39dd7c1
  Job Noorman authored Mar 23, 2023
  c39dd7c1
Feb 24, 2023
- [RISCV] Add vendor-defined XTheadCondMov (conditional move) extension · f68f04d0
  Philipp Tomsich authored Feb 24, 2023
  f68f04d0
- [RISCV] Add vendor-defined XTheadFMemIdx (FP Indexed Memory Operations) extension · 7b79e8d4
  Manolis Tsamis authored Feb 24, 2023
  7b79e8d4
- [RISCV] Add vendor-defined XTheadMemIdx (Indexed Memory Operations) extension · f6262201
  Manolis Tsamis authored Feb 24, 2023
  f6262201
Feb 22, 2023
- [RISCV] Add vendor-defined XTheadSync (Multi-core synchronization) extension · 16a6cf6a
  Manolis Tsamis authored Feb 22, 2023
  16a6cf6a
- [RISCV] Add vendor-defined XTheadCmo (Cache Management Operations) extension · f5b484c5
  Manolis Tsamis authored Feb 22, 2023
  f5b484c5
Feb 21, 2023
- [RISCV] Add vendor-defined XTheadMemPair (two-GPR Memory Operations) extension · bbb58a23
  Manolis Tsamis authored Feb 21, 2023
  bbb58a23
Feb 17, 2023
- [RISCV] Use MCSubtargetInfo::hasFeature where possible. NFC · 34aff475
  Craig Topper authored Feb 17, 2023
  34aff475
- Revert "[RISCV] Add vendor-defined XTheadMemPair (two-GPR Memory Operations) extension" · 16a66af0
  Philipp Tomsich authored Feb 17, 2023
  16a66af0
- [RISCV] Add vendor-defined XTheadMemPair (two-GPR Memory Operations) extension · d2918544
  Manolis Tsamis authored Feb 13, 2023
  d2918544
Feb 14, 2023
- [RISCV] Add vendor-defined XTheadMAC (multiply-accumulate) extension · d4012bc4
  Manolis Tsamis authored Feb 14, 2023
  d4012bc4
Feb 13, 2023
- [RISCV] Add vendor-defined XTheadBb (basic bit-manipulation) extension · fc02eeb2
  Philipp Tomsich authored Feb 13, 2023
  fc02eeb2
- [RISCV] Add vendor-defined XTHeadBs (single-bit) extension · 04a2baf5
  Philipp Tomsich authored Feb 13, 2023
  04a2baf5
Feb 08, 2023
- Revert "[RISCV] Add vendor-defined XTHeadBs (single-bit) extension" · 0bda1992
  Philipp Tomsich authored Feb 08, 2023
  0bda1992
- Revert "[RISCV] Add vendor-defined XTheadBb (basic bit-manipulation) extension" · b0c31322
  Philipp Tomsich authored Feb 08, 2023
  b0c31322
- [RISCV] Add vendor-defined XTheadBb (basic bit-manipulation) extension · 19a59099
  Philipp Tomsich authored Jan 31, 2023
  19a59099
- [RISCV] Add vendor-defined XTHeadBs (single-bit) extension · 656188dd
  Philipp Tomsich authored Jan 30, 2023
  656188dd
- [RISCV] Add vendor-defined XTHeadBa (address-generation) extension · e25b30d9
  Philipp Tomsich authored Feb 08, 2023
  e25b30d9
Feb 07, 2023
- [RISCV] Refactor RISCVDisassembler::getInstruction to remove repeated code. NFC · c7449c17
  Craig Topper authored Feb 06, 2023
  c7449c17
Feb 06, 2023
- [RISCV] Remove DecoderMethod from C_NOP_HINT. NFC · 2398e205
  Craig Topper authored Feb 06, 2023
  2398e205
- [RISCV][NFC] Update debug message for XTHeadVdot · ba8b8a73
  Philipp Tomsich authored Feb 04, 2023
  ba8b8a73
- [RISCV] Use uint32_t intead of uint64_t for instruction fields in RISCVDisassembler.cpp. NFC · 3a606785
  Craig Topper authored Feb 05, 2023
  3a606785