Commits · 283b4d6ba3119730e1722e8d78974b2c29d2492a · Roger Ferrer / llvm-epi · GitLab

Oct 08, 2020
- [GlobalISel] Add G_VECREDUCE_* opcodes for vector reductions. · 283b4d6b
  Amara Emerson authored Oct 02, 2020
  283b4d6b
- AArch64: treat MC expressions as 2s complement arithmetic. · 38348fa2
  Tim Northover authored Sep 22, 2020
  38348fa2
Oct 07, 2020
- [SVE] Add legalisation tests to sve-fixed-length-fp-reduce.ll · 365ef499
  Cameron McInally authored Oct 07, 2020
  
  365ef499
- [llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics. · 322d0afd
  Amara Emerson authored Oct 02, 2020
  322d0afd
- [SVE] Lower fixed length VECREDUCE_OR operation · 333b2ab6
  Cameron McInally authored Oct 07, 2020
  333b2ab6
Oct 06, 2020
- [SVE] Lower fixed length vector fneg and fsqrt operations. · 27f3d51b
  Paul Walker authored Oct 01, 2020
  27f3d51b
- [SVE] Lower fixed length vector floating point rounding operations. · 8bb702a8
  Paul Walker authored Oct 01, 2020
  8bb702a8
- [SVE][CodeGen] Fix DAGCombiner::ForwardStoreValueToDirectLoad for scalable vectors · 4ed47d50
  David Sherwood authored Sep 03, 2020
  4ed47d50
Oct 05, 2020
- [SVE] Add legalisation tests to sve-fixed-length-int-reduce.ll · 6bec45e2
  Cameron McInally authored Oct 05, 2020
  
  6bec45e2
- [SVE][CodeGen] Fix TypeSize/ElementCount related warnings in sve-split-store.ll · fa029308
  David Sherwood authored Aug 26, 2020
  fa029308
- [SVE] Lower fixed length VECREDUCE_AND operation · 9642ded8
  Cameron McInally authored Oct 05, 2020
  9642ded8
Oct 03, 2020
- [AArch64] Prefer prologues with sp adjustments merged into stp/ldp for WinCFI,... · 7d074057
  Martin Storsjö authored Sep 23, 2020
  7d074057
- [AArch64] Allow pairing lr with other GPRs for WinCFI · 890af2f0
  Martin Storsjö authored Sep 23, 2020
  890af2f0
- [AArch64] Match the windows canonical callee saved register order · 3780a4e5
  Martin Storsjö authored Sep 23, 2020
  3780a4e5
Oct 02, 2020
- Relax newly added opcode alias check to check only for a number instead of a specific opcode. · 24f406e6
  Douglas Yung authored Oct 02, 2020
  
  24f406e6
- Update legalizer-info-validation.mir test to test all opcodes. · 1e020b2a
  Amara Emerson authored Oct 02, 2020
  1e020b2a
- [AArch64] Generate dot for v16i8 sum reduction to i32 · f1925949
  Vinay Madhusudan authored Oct 02, 2020
  f1925949
- [AArch64] Omit SEH directives for the epilogue if none are needed · afb4e0f2
  Martin Storsjö authored Oct 01, 2020
  afb4e0f2
- [AArch64][SVE] Add lowering for llvm fabs · aab6f7db
  Muhammad Asif Manzoor authored Oct 01, 2020
  aab6f7db
- [GlobalISel][AArch64] Don't emit cset for G_FCMPs feeding into G_BRCONDs · 5402d11b
  Jessica Paquette authored Sep 30, 2020
  5402d11b
- [AArch64][GlobalISel] Use emitTestBit in selection for G_BRCOND · 8e8664e5
  Jessica Paquette authored Oct 01, 2020
  8e8664e5
- [AArch64][GlobalISel] Alias rules for G_FCMP to G_ICMP. · 017b8715
  Amara Emerson authored Oct 01, 2020
  017b8715
Oct 01, 2020
- [AArch64][GlobalISel] Make <8 x s8> integer arithmetic ops legal. · e28c5899
  Amara Emerson authored Oct 01, 2020
  
  e28c5899
- [AArch64][GlobalISel] Make <8 x s8> shifts legal and add selection support. · a97e97fa
  Amara Emerson authored Oct 01, 2020
  
  a97e97fa
- Revert "[AArch64][GlobalISel] Make <8 x s8> shifts legal." · 9a2b3bbc
  Amara Emerson authored Oct 01, 2020
  9a2b3bbc
- [AArch64][GlobalISel] Make <8 x s8> shifts legal. · 8071c2f5
  Amara Emerson authored Oct 01, 2020
  
  8071c2f5
- [AArch64][GlobalISel] Merge G_SHL, G_ASHR and G_LSHR legalizer rules together. · 9f6acb13
  Amara Emerson authored Oct 01, 2020
  9f6acb13
- [AArch64][GlobalISel] Use custom legalization for G_TRUNC for v8i8 vectors. · 73457536
  Amara Emerson authored Sep 23, 2020
  73457536
- [AArch64][GlobalISel] Camp oversize v4s64 G_FPEXT operations. · 4c265ce6
  Amara Emerson authored Oct 01, 2020
  
  4c265ce6
- [AArch64] Don't merge sp decrement into later stores when using WinCFI · f4b9dfd9
  Martin Storsjö authored Sep 29, 2020
  f4b9dfd9
- [SVE][CodeGen] Lower scalable fp_extend & fp_round operations · fcf70e1e
  Kerry McLaughlin authored Oct 01, 2020
  fcf70e1e
- [SVE][CodeGen] Legalisation of integer -> floating point conversions · 75db7cf7
  Kerry McLaughlin authored Sep 30, 2020
  75db7cf7
- [AArch64][GlobalISel] Select all-zero G_BUILD_VECTOR into a zero mov. · da11479f
  Amara Emerson authored Sep 18, 2020
  da11479f
- [AArch64][GlobalISel] Clamp oversize FP arithmetic vectors. · 196c097b
  Amara Emerson authored Sep 30, 2020
  
  196c097b
- [AArch64][GlobalISel] Add some more legal types for G_PHI, G_IMPLICIT_DEF, G_FREEZE. · 4ab45cc2
  Amara Emerson authored Sep 30, 2020
  4ab45cc2
- [AArch64][GlobalISel] NFC: Refactor G_FCMP selection code · bc43ddf4
  Jessica Paquette authored Sep 29, 2020
  bc43ddf4
Sep 30, 2020
- [AArch64] Avoid pairing loads when the base reg is modified · 8d8cb1ad
  Congzhe Cao authored Sep 30, 2020
  8d8cb1ad
- Reapply "RegAllocFast: Rewrite and improve" · 89baeaef
  Matt Arsenault authored Sep 22, 2020
  89baeaef
- [GlobalISel] Fix multiply with overflow intrinsics legalization generating invalid MIR. · 1d54e75c
  Amara Emerson authored Sep 29, 2020
  1d54e75c
Sep 29, 2020
- [SVE] Lower fixed length VECREDUCE_[FMAX|FMIN] to Scalable · 80381c4d
  Cameron McInally authored Sep 29, 2020
  80381c4d