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  1. Mar 06, 2017
  2. Mar 05, 2017
    • Ed Schouten's avatar
      Drop the dependency on dl_unwind_find_exidx(). · fa1ef7d8
      Ed Schouten authored
      While porting libunwind over to CloudABI for ARMv6, I observed that this
      source file doesn't build, as it depends on dl_unwind_find_exidx(),
      which CloudABI's C library was lacking. After I added that function, I
      still needed to patch up libunwind to define _Unwind_Ptr.
      
      Taking a step back, I wonder why we need to make use of this function
      anyway. The unwinder already has some nice code to use dl_iterate_phdr()
      to scan for a PT_GNU_EH_FRAME header. The dl_unwind_find_exidx() does
      the same thing, except matching PT_ARM_EXIDX instead. We could also do
      that ourselves.
      
      This change gets rid of the dl_unwind_find_exidx() call and extends the
      dl_iterate_phdr() loop. This approach has the advantage of getting rid
      of some of those OS-specific #ifdefs. This now means that if an
      operating system only provides dl_iterate_phdr(), it gets support for
      unwinding on all architectures. There is no need to add more stuff, just
      to get ARMv6 support.
      
      This change is identical to r295944, except that it now adds the
      necessary code to do bounds checking on PT_LOAD. The previous version of
      this change lacked this, which didn't cause any problems on CloudABI,
      but did break the Linux build bots. This is why I reverted it in
      r295948.
      
      Differential Revision:	https://reviews.llvm.org/D30306
      
      llvm-svn: 296991
      fa1ef7d8
    • Craig Topper's avatar
      [APInt] Remove the And/Or/Xor/Not functions from the APIntOps namespace. · 71db98c6
      Craig Topper authored
      Summary:
      They aren't used anywhere in tree and its preferable to use the &, |, ^, or ~ operators.
      
      With my patch to add rvalue reference support to &, |, ^ operators it also becomes less performant to use these functions.
      
      Reviewers: RKSimon, davide, hans
      
      Reviewed By: RKSimon
      
      Subscribers: llvm-commits
      
      Differential Revision: https://reviews.llvm.org/D30613
      
      llvm-svn: 296990
      71db98c6
    • Simon Pilgrim's avatar
      [SelectionDAG] Fix vector splitting for *_EXTEND_VECTOR_INREG instructions · 584d6d9d
      Simon Pilgrim authored
      Found by fuzz testing after rL296985 landed
      
      llvm-svn: 296989
      584d6d9d
    • Tobias Grosser's avatar
      New Test-Case for Region Analysis · 495ad0b2
      Tobias Grosser authored
      
      
      While working on improvements to the region info analysis, this test case caused
      an incorrect region 1 => 2 to be detected.  It is incorrect because entry has an
      outgoing edge to 3.  This is interesting because 1 dom 2 and 2 pdom 1, which
      should have been enough to prevent incoming forward edges into the region and
      outgoing forward edges from the region.
      
      Reviewers: grosser
      
      Subscribers: llvm-commits
      
      Contributed-by: default avatarNandini Singhal <cs15mtech01004@iith.ac.in>
      
      Differential Revision: https://reviews.llvm.org/D30603
      
      llvm-svn: 296988
      495ad0b2
    • Benjamin Kramer's avatar
      [X86] Silence GCC enum compare warning. · bb635e03
      Benjamin Kramer authored
      X86ISelLowering.cpp:26506:36: error: enumeral mismatch in conditional
      expression: 'llvm::X86ISD::NodeType' vs 'llvm::ISD::NodeType'
      [-Werror=enum-compare]
      
      llvm-svn: 296986
      bb635e03
    • Simon Pilgrim's avatar
      [X86][SSE] Lower 128-bit vectors to SIGN/ZERO_EXTEND_VECTOR_IN_REG ops · 9f5c251d
      Simon Pilgrim authored
      As described on PR31712, we miss a variety of legalization combines because we lower these to X86ISD::VSEXT/VZEXT despite them having the same functionality. This patch makes 128-bit (SSE41) SIGN/ZERO_EXTEND_VECTOR_IN_REG ops legal, adds the necessary tablegen plumbing and uses a helper 'getExtendInVec' to decide when to use SIGN/ZERO_EXTEND_VECTOR_IN_REG or VSEXT/VZEXT.
      
      We're missing a couple of shuffle combines that will be added in a future patch for review.
      
      Later patches can then support the AVX2 cases as a mixture of SIGN/ZERO_EXTEND and SIGN/ZERO_EXTEND_VECTOR_IN_REG, and then finally deal with the AVX512 cases.
      
      Differential Revision: https://reviews.llvm.org/D30549
      
      llvm-svn: 296985
      9f5c251d
    • Sylvestre Ledru's avatar
      Revert commit r296967, no typo · 4bc8292a
      Sylvestre Ledru authored
      llvm-svn: 296984
      4bc8292a
    • Craig Topper's avatar
      [SimplifyCFG] Use APInt::operator| instead of APInt::Or. NFC · b9dbd4d5
      Craig Topper authored
      I'm looking to improve operator| to support rvalue references and may remove APInt::Or.
      
      llvm-svn: 296982
      b9dbd4d5
    • Craig Topper's avatar
      [DAGCombine] Use APInt::operator|(uint64_t) instead of creating a temporary... · 6ffc044b
      Craig Topper authored
      [DAGCombine] Use APInt::operator|(uint64_t) instead of creating a temporary APInt and calling APInt::Or. NFC
      
      This is more efficient by itself. But this is prep for a future patch that may remove APInt::Or while making operator| support rvalue references similar to add/sub.
      
      llvm-svn: 296981
      6ffc044b
  3. Mar 04, 2017
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