Commits · 3be1ae24fb17bf90cb3d8fc8e83ebd9d4523a594 · Roger Ferrer / llvm-epi · GitLab

Feb 07, 2023
- [CodeGen] Add standard print/debug utilities to MVT · 3be1ae24
  Philip Reames authored Feb 07, 2023
  3be1ae24
- [X86] combineX86ShufflesRecursively - peek through insert_subvector(undef, x,... · 16a357f6
  Simon Pilgrim authored Feb 07, 2023
  16a357f6
- [X86] combineX86ShuffleChainWithExtract - refactor to remove need to widen all vectors · 3daf2fb7
  Simon Pilgrim authored Feb 07, 2023
  3daf2fb7
- [ARM] Perform lane interleaving from reductions. · f634096f
  David Green authored Feb 07, 2023
  f634096f
- [NFC][TargetParser] Remove llvm/ADT/Triple.h · 62c7f035
  Archibald Elliott authored Feb 07, 2023
  62c7f035
- [CodeGen] Make more use of MachineOperand::getOperandNo. NFC. · a07584d5
  Jay Foad authored Feb 03, 2023
  a07584d5
- [AMDGPU] Remove the unused u8imm operand definition. · 3d6b108a
  Ivan Kosarev authored Feb 07, 2023
  3d6b108a
- [AArch64][SME2] Add multi-vector frint intrinsics · f3188b98
  Kerry McLaughlin authored Feb 07, 2023
  f3188b98
- [AArch64][SME2] Add multi-vector floating point min/max number intrinsics · 38599210
  Kerry McLaughlin authored Feb 07, 2023
  38599210
- [NFC][TargetParser] Remove llvm/Support/TargetParser.h · 8e3d7cf5
  Archibald Elliott authored Feb 07, 2023
  
  8e3d7cf5
- [NFC][TargetParser] Remove llvm/Support/CSKYTargetParser.h · b9a1c4d5
  Archibald Elliott authored Feb 03, 2023
  
  b9a1c4d5
- [NFC][TargetParser] Remove llvm/Support/ARMTargetParser.h · 27aeb58c
  Archibald Elliott authored Feb 03, 2023
  
  27aeb58c
- [ARM] Remove reduce(shuffle) if all the lanes are used · 734d113a
  David Green authored Feb 07, 2023
  734d113a
- [ARM] Add various tests for reductions of shuffles. NFC · dfe11c00
  David Green authored Feb 07, 2023
  
  dfe11c00
- [RISCV] Refactor RISCVDisassembler::getInstruction to remove repeated code. NFC · c7449c17
  Craig Topper authored Feb 06, 2023
  c7449c17
- MIPS: fix build from IR files, nan2008 and FpAbi · b4b95dee
  YunQiang Su authored Feb 06, 2023
  b4b95dee
- [AArch64][SVE] Fix crash for DestructiveBinaryCommWithRev zero merging · 341b1df5
  zhongyunde authored Feb 07, 2023
  341b1df5
- [AArch64][SVE] Replace destructive operand of vector zeros with a bundled MOVPRFX instruction · 39af4659
  zhongyunde authored Feb 07, 2023
  39af4659
- [AArch64][GlobalISel] Widen G_ADD/G_MUL/G_OR/... element types if size < 8b · 5e33e301
  Vladislav Dzhidzhoev authored Jan 26, 2023
  5e33e301
Feb 06, 2023
- Revert "[AArch64][GlobalISel] Widen G_ADD/G_MUL/G_OR/... element types if size < 8b" · 96bd3649
  Vladislav Dzhidzhoev authored Feb 06, 2023
  96bd3649
- [AArch64][GlobalISel] Widen G_ADD/G_MUL/G_OR/... element types if size < 8b · 254e2ad8
  Vladislav Dzhidzhoev authored Jan 26, 2023
  254e2ad8
- Only match BMI (BLSR, BLSI, BLSMSK) if the add/sub op is single use · 725b72c1
  Noah Goldstein authored Feb 06, 2023
  725b72c1
- Search through associative operators for BMI patterns (BLSI, BLSR, BLSMSK) · 3857d9de
  Noah Goldstein authored Feb 06, 2023
  3857d9de
- Match (xor TSize - 1, ctlz) to `bsr` instead of `lzcnt` + `xor` · cf8fadcf
  Noah Goldstein authored Feb 06, 2023
  cf8fadcf
- [AMDGPU][NFC] Clean up the VOP profile definition for v_swap_b32. · 84a07dcf
  Ivan Kosarev authored Feb 06, 2023
  84a07dcf
- [X86] combineConcatVectorOps - add X86ISD::VPERMV handling · 2cf31ba5
  Simon Pilgrim authored Feb 06, 2023
  
  2cf31ba5
- [X86] combineConcatVectorOps - merge 256-bit logic ops on AVX2+ · 505cf2b6
  Simon Pilgrim authored Feb 06, 2023
  505cf2b6
- [X86] Change precision control to FP80 during u64->fp32 conversion on Windows. · 11fb09ec
  Craig Topper authored Feb 06, 2023
  11fb09ec
- [RISCV] Remove DecoderMethod from C_NOP_HINT. NFC · 2398e205
  Craig Topper authored Feb 06, 2023
  2398e205
- [RISCV] Make 'c.addi x0, imm' an alias for 'c.nop imm'. · 638abc27
  Craig Topper authored Feb 06, 2023
  638abc27
- [AArch64] Don't create ST2 for 64bit store that requires an EXT · 120e9685
  David Green authored Feb 06, 2023
  120e9685
- Remove no longer needed includes of LegacyPassManager.h · 2dd221fe
  Bjorn Pettersson authored Feb 06, 2023
  2dd221fe
- AMDGPU/MC: Fix indentation and remove unused macro after D142636 · a256e1d9
  Petar Avramovic authored Feb 06, 2023
  
  a256e1d9
- [RISCV][NFC] Update debug message for XTHeadVdot · ba8b8a73
  Philipp Tomsich authored Feb 04, 2023
  ba8b8a73
- [NFC] Inline variable · 80eacb1b
  Guillaume Chatelet authored Feb 06, 2023
  
  80eacb1b
- [RISCV] Use uint32_t intead of uint64_t for instruction fields in RISCVDisassembler.cpp. NFC · 3a606785
  Craig Topper authored Feb 05, 2023
  3a606785
- [RISCV] Simplify some code in RISCVDisassembler. NFC · d2fd0d3c
  Craig Topper authored Feb 05, 2023
  d2fd0d3c
- AMDGPU: Mark control flow intrinsics non-duplicable · be3f4591
  Ruiling Song authored Feb 02, 2023
  be3f4591
- Revert "[clang][WebAssembly] Initial support for reference type externref in clang" · bccf5999
  Vitaly Buka authored Feb 05, 2023
  bccf5999
- [X86] Add RMPQUERY to SNP instructions · 10b7c47e
  Ganesh Gopalasubramanian authored Feb 06, 2023
  10b7c47e