Commits · 47b7f33b13b698575432fabc5010c79a0c384b19 · Roger Ferrer / llvm-epi · GitLab

Sep 27, 2023
- [IR] Allow llvm.ptrmask of vectors (#67434) · 47b7f33b
  Nikita Popov authored Sep 27, 2023
  47b7f33b
- [X86] IsNOT - fold PCMPGT(C, X) -> PCMPGT(X,C-1) · 57b0194b
  Simon Pilgrim authored Sep 27, 2023
  57b0194b
- [AMDGPU] Test codegen'ing True16 additions. · be8b5599
  Ivan Kosarev authored Jul 21, 2023
  be8b5599
- [AMDGPU][True16] Pre-commit addition tests. · 3ff7d51e
  Ivan Kosarev authored Jul 28, 2023
  3ff7d51e
- [AArch64] Enable "sink-and-fold" in MachineSink by default (#67432) · ace20e24
  Momchil Velikov authored Sep 27, 2023
  
  ace20e24
- Revert "[NVPTX] Add support for maxclusterrank in launch_bounds (#66496)" · 0afbcb20
  Sam McCall authored Sep 27, 2023
  0afbcb20
- [RISCV] Support select/merge like ops for fp16 vectors when only have Zvfhmin · 5278cc36
  Jianjian GUAN authored Aug 29, 2023
  5278cc36
- [NVPTX] Add support for maxclusterrank in launch_bounds (#66496) · dfab31b4
  Jakub Chlanda authored Sep 27, 2023
  dfab31b4
- [RISCV] Support fmaximum/fminimum for fp16 vector when only Zvfhmin enabled (#67393) · d6b1b998
  Jim Lin authored Sep 27, 2023
  d6b1b998
- [RISCV] Promote SETCC and VP_SETCC of f16 vectors when only have zvfhmin (#66866) · 435da4ef
  Jianjian GUAN authored Sep 27, 2023
  435da4ef
- [TargetLowering] fix index OOB (#67494) · 35a364fa
  Nick Desaulniers authored Sep 26, 2023
  35a364fa
- [x86] precommit test conversion via update_llc_test_checks.py (#67463) · 2e2c61eb
  Nick Desaulniers authored Sep 26, 2023
  2e2c61eb
Sep 26, 2023
- [RISCV] Correct Zhinx load/store patterns to use AddrRegImm. · b26157ed
  Craig Topper authored Sep 26, 2023
  
  b26157ed
- [RISCV] Autogenerate tests to add missing CHECK lines. NFC · 9eebfa80
  Craig Topper authored Sep 26, 2023
  
  9eebfa80
- Move test split-deadloop.mir that was added in e3d714f2 to AArch64 directory instead of ARM. · 6716d3dd
  Douglas Yung authored Sep 26, 2023
  
  6716d3dd
- [AMDGPU] Add gfx1150 test coverage in trans-forwarding-hazards.mir · e3d714f2
  Jay Foad authored Sep 26, 2023
  e3d714f2
- [AArch64] A few extra rshrn intrinsic tests. NFC · b10721e9
  David Green authored Sep 26, 2023
  
  b10721e9
- [AArch64] Bail out of HomogeneousPrologEpilog for functions with swif… (#67417) · baf39032
  Zhaoxuan Jiang authored Sep 26, 2023
  baf39032
- [RA] Don't split a register generated from another split (#67351) · 31f81e96
  weiguozhi authored Sep 26, 2023
  31f81e96
- [RISCV] Transform build_vector((binop X_i, C_i)..) to binop (build_vector, build_vector) (#67358) · e39add89
  Philip Reames authored Sep 26, 2023
  e39add89
- [AArch64] Handle scalable vectors in combineFMulOrFDivWithIntPow2. · 03647e2e
  David Green authored Sep 26, 2023
  03647e2e
- [SPIRV] Add OpAccessChain instruction support (#66253) · c01b5bbb
  Nathan Gauër authored Sep 26, 2023
  c01b5bbb
- [AMDGPU] Fix passing CodeGen/AMDGPU/frem.ll on gfx1150. (#67425) · 64482d57
  Ivan Kosarev authored Sep 26, 2023
  64482d57
- [AMDGPU] Remove the support for non-True16 copies between different register sizes. · 287f6cdd
  Ivan Kosarev authored Jul 21, 2023
  287f6cdd
- [MachineLICM] Handle Subloops · ff68e43c
  Jingu Kang authored Jul 20, 2023
  ff68e43c
- [AArch64] Limit immediate offsets when folding instructions into addressing modes (#67345) · fe763d8a
  Momchil Velikov authored Sep 26, 2023
  fe763d8a
- Revert "[SimplifyCFG] Transform for redirecting phis between unmergeable BB and SuccBB (#67275)" · 431969ed
  Muhammad Omair Javaid authored Sep 26, 2023
  431969ed
- Reland https://reviews.llvm.org/D159073 . · d7195c57
  esmeyi authored Sep 26, 2023
  d7195c57
- [AArch64] Additional testing for i128 and non-temporal loads/stores undef BE. NFC · cab01a8b
  David Green authored Sep 26, 2023
  
  cab01a8b
- [AMDGPU] New image intrinsic optimizer pass (#67151) · d85d143a
  Jay Foad authored Sep 26, 2023
  d85d143a
- [PowerPC] Add test to show wrong target flags printed at MO_TLSGDM_FLAG operand. NFC. · 5fabc8ba
  Kai Luo authored Sep 26, 2023
  
  5fabc8ba
- [RISCV] Add searchable table for tune information (#66193) · 08165c44
  Pengcheng Wang authored Sep 26, 2023
  08165c44
- [LoongArch] Improve codegen for i8/i16 'atomicrmw xchg a, {0,-1}' · 6417ce43
  WANG Rui authored Sep 26, 2023
  6417ce43
- [LoongArch] Add test cases for atomicrmw xchg {0,-1} {i8,i16} · 555e2397
  WANG Rui authored Sep 26, 2023
  555e2397
- Revert "[PowerPC][Peephole] Combine rldicl/rldicr and andi/andis after isel." · 77147a95
  esmeyi authored Sep 25, 2023
  77147a95
- [PowerPC][Peephole] Combine rldicl/rldicr and andi/andis after isel. · 2de74e1b
  esmeyi authored Sep 25, 2023
  2de74e1b
- [RISCV] Fix the float value to test constantpool lowering under differe… (#67297) · 5e1f5f47
  Jim Lin authored Sep 26, 2023
  5e1f5f47
- [RISCV][GISel] Add RegBank selection for G_SMULH (#67381) · de17384c
  Min-Yih Hsu authored Sep 25, 2023
  de17384c
- [RISCV][GISel] Add instruction selection for G_SEXT, G_ZEXT, and G_SEXT_INREG (#67359) · 0d7c340c
  Min-Yih Hsu authored Sep 25, 2023
  0d7c340c
Sep 25, 2023
- [NVPTX] Improve lowering of v2i16 logical ops. (#67365) · 671e2ba4
  Artem Belevich authored Sep 25, 2023
  671e2ba4