Commits · 5c7ec998a916baf8b35d571d0cc11753d464792d · Roger Ferrer / llvm-epi · GitLab

May 11, 2022
- [RISCV] Fold addiw from (add X, (addiw (lui C1, C2))) into load/store address · 5c7ec998
  Craig Topper authored May 11, 2022
  5c7ec998
- [test, riscv] Add test illustrating missing handling for fallthrough blocks in 541c9ba8 · ca81c0f8
  Philip Reames authored May 11, 2022
  
  ca81c0f8
- [RISCV] Add caching to the gather/scatter to strided load/store conversion. · f499ec6b
  Craig Topper authored May 11, 2022
  f499ec6b
- [RISCV] Override TargetLowering::shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd. · 0ebb02b9
  Craig Topper authored May 11, 2022
  0ebb02b9
- [RISCV] Add a DAG combine to pre-promote (i32 (and (srl X, Y), 1)) with Zbs on RV64. · 07817427
  Craig Topper authored May 11, 2022
  07817427
- [riscv] Canonicalize vsetvli (vsetvli avl, vtype1) vtype2 transitionsas reviewed · 72925d98
  Philip Reames authored May 11, 2022
  72925d98
- [riscv] Add tests for vsetvli reuse across iterations of a loop · 98736234
  Philip Reames authored May 11, 2022
  98736234
- [RISCV] Remove some TODOs in tests · b049eb1f
  Shao-Ce SUN authored May 10, 2022
  b049eb1f
- [riscv] Prefer to use previous VL for scalar move instructionsK · cc0283a6
  Philip Reames authored May 11, 2022
  cc0283a6
- [RISCV] Make PseudoReadVL have the vtypes of the corresponding VLEFF/VLSEGFF. · 4537aae0
  Yeting Kuo authored May 08, 2022
  4537aae0
- [RISCV] Add rvv codegen support for vp.fpext. · 2509dcd5
  Jianjian GUAN authored Apr 18, 2022
  2509dcd5
May 10, 2022
- Revert "[RISCV][SelectionDAG] Support VECREDUCE_ADD mask operation" · f14a1f26
  Lian Wang authored May 10, 2022
  f14a1f26
- [RISCV][SelectionDAG] Support VECREDUCE_ADD mask operation · 17a8a1bb
  Lian Wang authored May 09, 2022
  17a8a1bb
- [RISCV] Add more tests for vector reduce mask operations · 3b3ff240
  Lian Wang authored May 10, 2022
  3b3ff240
May 09, 2022
- [riscv] Add a few more vsetvli insertion tests · 11728db9
  Philip Reames authored May 09, 2022
  11728db9
- [riscv] Fix state tracking bug on vsetvli (phi of vsetvli) peephole · 7ed16e7c
  Philip Reames authored May 09, 2022
  7ed16e7c
May 07, 2022
- [RISCV] Regenerate rv32zbp-zbkb.ll · a385645b
  Simon Pilgrim authored May 07, 2022
  a385645b
May 06, 2022
- [RISCV] Add an extra vsetvli insertion test · 588155aa
  Fraser Cormack authored May 06, 2022
  588155aa
- [RISCV] Enable MachineOutliner by default under -Oz for RISCV · 4ff5e818
  Pengcheng Wang authored May 06, 2022
  4ff5e818
- [RISCV][SelectionDAG] Support VP_REDUCE_ADD mask operation. · fb0d636f
  Lian Wang authored May 05, 2022
  fb0d636f
May 05, 2022
- [DAGCombiner] Fold (sext/zext undef) -> 0 and aext(undef) -> undef. · 4e2d1a6c
  Craig Topper authored May 05, 2022
  4e2d1a6c
- [DAGCombiner] Fold (max/min X, X) -> X. · fd13192a
  Craig Topper authored May 04, 2022
  fd13192a
- [RISCV] Add integer min/max intrinsic tests. NFC · be51ddf6
  Craig Topper authored May 04, 2022
  be51ddf6
- [riscv] Use X0 for destination of VSETVLI instruction if result unused · 042a7a5f
  Philip Reames authored May 05, 2022
  042a7a5f
- [RISCV] Use movImm went multiplying by simm12 in getVLENFactoredAmount. · 60cb4896
  Craig Topper authored May 04, 2022
  60cb4896
May 04, 2022
- [RISCV] Add a special case to treat riscv-v-vector-bits-min=-1 as meaning use Zvl*b value. · 411bb42e
  Craig Topper authored May 04, 2022
  411bb42e
- [RISCV] Add a test showing incorrect VSETVLI insertion · 78c1dcbf
  Fraser Cormack authored Apr 20, 2022
  78c1dcbf
- [RISCV] Update isLegalAddressingMode for RVV. · 1d6430b9
  Craig Topper authored May 03, 2022
  1d6430b9
- [RISCV] Make use of SHXADD instructions in RVV spill/reload code. · 9cce9a12
  Craig Topper authored May 03, 2022
  9cce9a12
- [riscv] Add vsetvli tests involving moves to/from scalar regs · dbe716e8
  Philip Reames authored May 03, 2022
  
  dbe716e8
- [riscv] Add a couple more vsetvli tests · dbbbc9e2
  Philip Reames authored May 03, 2022
  
  dbbbc9e2
May 03, 2022
- [RISCV] Precommit test cases for (uaddo X, C) · 3baff808
  Hsiangkai Wang authored Apr 28, 2022
  3baff808
- [RISCV] Add isCommutable to FADD/FMUL/FMIN/FMAX/FEQ. · 72a66358
  Craig Topper authored May 02, 2022
  72a66358
- [RISCV] Fix incorrect codegen for masked vmsge{u}.vx with mask agnostic. · 5807e59a
  Zakk Chen authored May 02, 2022
  5807e59a
- [DAGCombiner] reassociationCanBreakAddressingModePattern should check uses of the outer add. · 5f057eaa
  Craig Topper authored May 02, 2022
  5f057eaa
Apr 30, 2022
- [DAGCombiner] When matching a disguised rotate by constant don't forget to apply LHSMask/RHSMask. · 6affe87b
  Craig Topper authored Apr 30, 2022
  6affe87b
- [RISCV][AArch64] Pre-commit tests for D124711. NFC · 808c33ac
  Craig Topper authored Apr 30, 2022
  
  808c33ac
- [RISCV] Don't getDebugLoc for the end node of MBB iterator · e098281c
  luxufan authored Apr 30, 2022
  e098281c
- [RISCV] Add DAGCombine to fold base operation and reduction. · c069e370
  Yeting Kuo authored Mar 27, 2022
  c069e370
- [RISCV] Copy test from mem.ll to mem64.ll for completeness. NFC · 23b7e15c
  Craig Topper authored Apr 29, 2022
  23b7e15c