We don't catch this with target shuffle simplification if the src/dst types are different.

llvm-svn: 347386

llvm-svn: 347385

llvm-svn: 347384

Add pthread_tryjoin_np() and pthread_timedjoin_np() interceptors on Linux,
so that ThreadSanitizer can handle programs using these functions.

Author: Yuri Per (yuri)
Reviewed in: https://reviews.llvm.org/D54521

llvm-svn: 347383

llvm-svn: 347382

llvm-svn: 347381

[X86] In getScalarMaskingNode, replace scalar_to_vector with a bitcast to v8i1 and an extract_subvector to convert i8 to v1i1.

The bitcast can be nicely merged with any i8 loads that exist for argument passing in 32 mode for example.

llvm-svn: 347380

LVI was symbolically executing binary operators only when the RHS was
constant, missing the case where we have a ConstantRange for the RHS,
but not an actual constant. Tested using check-all and by
bootstrapping. Compile time is not impacted measurably.

Differential Revision: https://reviews.llvm.org/D19859

llvm-svn: 347379

Even though these deps weren't needed, this makes Fuchsia driver
better match other drivers, and it may be necessary when trying to
use different C libraries on Fuchsia.

Differential Revision: https://reviews.llvm.org/D54741

llvm-svn: 347378

Summary:
Avoid buffer overflow by replacing the pointer interface with an array reference interface in C++2a.
Tentatively ready on Batavia2018.

 https://wg21.link/lwg2499
 https://wg21.link/p0487

Reviewers: mclow.lists, ldionne, EricWF

Reviewed By: ldionne

Subscribers: libcxx-commits, cfe-commits, christof

Differential Revision: https://reviews.llvm.org/D51268

llvm-svn: 347377

We have efficient codegen on P9 for lowering bswap that involves moving
the value into a vector reg and moving it back. However, the check under
which we custom lowered it did not adequately reflect the actual requirements.
It required only that the subtarget be an implementation of ISA 3.0 since all
compliant implementations have to provide the vector instructions.
However, the kernel builds have a valid use case for -mno-altivec -mcpu=pwr9
(i.e. don't emit vector code, don't have to save vector regs for context
switch). So we should require the correct features for this lowering.
Fixes https://bugs.llvm.org/show_bug.cgi?id=39334

llvm-svn: 347376

[X86] Correct 256 vpmovzx/vpmovsx isel patterns to check HasAVX2 instead of HasAVX to prevent fast-isel from using them incorrectly.

These are AVX2 instructions, but have been incorrectly marked in tablegen for a while. This wasn't a problem until r346784 switched the patterns to use target independent ISD opcodes. This made the patterns visible to fast isel.

Fixes PR39733

llvm-svn: 347375

llvm-svn: 347374

This test examines the behavior change of clang::tooling::Diagnostic in r347372.

llvm-svn: 347373

These offsets are useless (and even harmful in certain cases) in exported
diagnostics. The test will be added to clang-tidy, since it's the main user of
the clang::tooling::Diagnostic class.

llvm-svn: 347372

llvm-svn: 347371

Reviewers: sbc100, dschuff

Subscribers: mehdi_amini, jgravelle-google, sunfish, steven_wu, dexonsmith, llvm-commits

Differential Revision: https://reviews.llvm.org/D54683

llvm-svn: 347370

llvm-svn: 347369

This change adds an end-to-end test that ensures FDR mode can be
re-initialised safely in the face of multiple threads being traced.

llvm-svn: 347368

The '-faligned-allocation' flag uses a feature with the same name (with a
leading dash).

llvm-svn: 347367

llvm-svn: 347366

llvm-svn: 347365

EvaluateAsInt() is sometimes called in a constant context. When that's the
case, we need to specify it as so.

llvm-svn: 347364

Aligning everything makes what we're doing more obvious.

llvm-svn: 347363

llvm-svn: 347362

We can't guarantee that demanded bits passing through the vector shuffle won't cause the AND in front of this to be removed. This would prevent the PACKUS from being matched during shuffle lowering.

Unfortunately, this adds a packuswb to one of the vector-reduce-mul.ll tests since we were removing the shuffle via SimplifyDemandedVectorElts. We appear to have similar issues with vpmovwb on the same test case on other targets.

llvm-svn: 347361

A couple of tests were broken when clang implemented the compiler parts of P0482 (support for char8_t). Comment out those bits until we implement the corresponding bits in libc++

llvm-svn: 347360

llvm-svn: 347359

llvm-svn: 347358

llvm-svn: 347357

  
This is another step in vector narrowing - a follow-up to D53784
(and hoping to eventually squash potential regressions seen in
D51553).

The x86 test diffs are wins, but the AArch64 diff is probably not.
That problem already exists independent of this patch (see PR39722), but it
went unnoticed in the previous patch because there were no regression tests
that showed the possibility.

The x86 diff in i64-mem-copy.ll is close. Given the frequency throttling
concerns with using wider vector ops, an extra extract to reduce vector
width is the right trade-off at this level of codegen.

Differential Revision: https://reviews.llvm.org/D54392

llvm-svn: 347356

Unit tests enabled only in platform tested.

Reviewers: krytarowski, vitalybuka

Reviewed By: krytarowski, vitalybuka

Differential Revision: https://reviews.llvm.org/D54739

llvm-svn: 347355

When you have a member function with a ref-qualifier, for example:

struct Foo {
  void Func() &;
  void Func2() &&;
};

clang-cl was not emitting this information. Doing so is a bit
awkward, because it's not a property of the LF_MFUNCTION type, which
is what you'd expect. Instead, it's a property of the this pointer
which is actually an LF_POINTER. This record has an attributes
bitmask on it, and our handling of this bitmask was all wrong. We
had some parts of the bitmask defined incorrectly, but importantly
for this bug, we didn't know about these extra 2 bits that represent
the ref qualifier at all.

Differential Revision: https://reviews.llvm.org/D54667

llvm-svn: 347354

This is for compatibility with MSVC, which also marks this pointers
as being const-qualified.

Fixes llvm.org/pr36526

Differential Revision: https://reviews.llvm.org/D54736

llvm-svn: 347353

Summary:
Similar to auto-completion for ObjC methods, inherited properties
should be penalized / direct class and category properties should
be prioritized.

Note that currently, the penalty for using a result from a base class
(CCD_InBaseClass) is equal to the penalty for using a method as a
property (CCD_MethodAsProperty).

Reviewers: jkorous, sammccall, akyrtzi, arphaman, benlangmuir

Reviewed By: sammccall, akyrtzi

Subscribers: arphaman, cfe-commits

Differential Revision: https://reviews.llvm.org/D53900

llvm-svn: 347352

This patch adjusts a test not to depend on deprecated FileCheck
behavior that permits overlapping matches within a block of CHECK-DAG
directives.  Thus, this patch also removes uses of FileCheck's
-allow-deprecated-dag-overlap command-line option.

There were two issues in this test:

1. There were sets of patterns for store instructions in which a
pattern X could match a superset of a pattern Y.  While X appeared
before Y, Y's intended match appeared before X's intended match.  The
result was that X matched Y's intended match.  Under the old
overlapping behavior, Y also matched Y's intended match.  Under the
new non-overlapping behavior, Y had nothing left to match.  This patch
fixes this by gathering these sets in one place and putting the most
specific patterns (Y) before the more general patterns (X).

2. The CHECK-DAG patterns involving the variables CBPADDR3 and
CBPADDR4 were the same, but there was only one match in the text, so
CBPADDR4 patterns had nothing to match under the new non-overlapping
behavior.  Moreover, a preceding related series of directives had
variables (SADDR0, BPADDR0, etc.) numbered only 0 through 4, but this
series had variables numbered 0 through 5.  Assuming CBPADDR4's
directives were not intended, this patch removes them.

Reviewed By: ABataev

Differential Revision: https://reviews.llvm.org/D54765

llvm-svn: 347351

This patch adjusts a test not to depend on deprecated FileCheck
behavior that permits overlapping matches within a block of CHECK-DAG
directives.  Thus, this patch also removes uses of FileCheck's
-allow-deprecated-dag-overlap command-line option.

Specifically, the FileCheck variables DBG_LOC_START, DBG_LOC_END, and
DBG_LOC_CANCEL were all set to the same value.  As a result, three
TERM_DEBUG-DAG patterns, one for each variable, all matched the same
text under the old overlapping behavior.  Under the new
non-overlapping behavior, that's not permitted.  This patch's solution
is to replace these variables with one variable and replace these
patterns with one pattern.

Reviewed By: ABataev

Differential Revision: https://reviews.llvm.org/D54764

llvm-svn: 347350

Don't use a uint32_t*, use a ulittle32_t* to make this correct
on big endian systems.

Patch by James Clarke
Differential Revision: https://reviews.llvm.org/D54421

llvm-svn: 347349

[X86] Emit a single shuffle for the v16i8->v4i32 step of a SIGN_EXTEND_VECTOR_INREG lowering on pre-sse4.1 targets.

Previously we emitted to separate shuffles, one for unpcklbw and one for unpcklwd. Instead emit a single shuffle equivalent to both of the original shuffles. Shuffle lowering seems able to handle it. This avoids a bitcast between the two shuffles which seems helpful to DAG combine.

Remove the custom type legalization for v8i8->v8i32. I had put that in to avoid some almost duplicate punpcklbw instructions I was seeing, but this lowering change seems to fix that. It also fixes some duplicate shuffles seen in vector-sext.ll

llvm-svn: 347348

GNU/Hurd provides standard Posix threads

Reviewed as https://reviews.llvm.org/D54339.
Thanks to Samuel Thibault for the patch.

llvm-svn: 347347