Commits · 6b76d82853fdc64160dda44610407c04af620292 · Roger Ferrer / llvm-epi · GitLab

Mar 12, 2021
- GlobalISel: Fix marking byval arguments as immutable · 6b76d828
  Matt Arsenault authored Mar 06, 2021
  6b76d828
- GlobalISel: Partially fix handling of byval arguments · 34471c30
  Matt Arsenault authored Mar 05, 2021
  34471c30
- AArch64/GlobalISel: Don't use common prefix in test · d44a3dad
  Matt Arsenault authored Mar 06, 2021
  d44a3dad
- [RISCV] Optimize INSERT_VECTOR_ELT sequences · 641f5700
  Fraser Cormack authored Mar 08, 2021
  641f5700
- [RISCV] Return false from isShuffleMaskLegal except for splats. · 1d26bbcf
  Craig Topper authored Mar 11, 2021
  1d26bbcf
- [AMDGPU] Do not annotate an else branch if there is a kill · f08dadd2
  Carl Ritson authored Mar 12, 2021
  f08dadd2
- [AMDGPU] Restrict image_msaa_load to MSAA dimension types · c07f2025
  Carl Ritson authored Mar 12, 2021
  c07f2025
- [AMDGPU] Don't check hasStackObjects() when reserving VGPR · e8e6817d
  Ruiling Song authored Mar 09, 2021
  e8e6817d
- [RISCV] Add test cases for fixed vector bitreverse, bswap, ctlz, cttz, and ctpop. · 2ac7a3cf
  Craig Topper authored Mar 11, 2021
  2ac7a3cf
Mar 11, 2021
- [SelectionDAG] Improve scalarization of irregular vector types · cfe69c8e
  LemonBoy authored Mar 11, 2021
  cfe69c8e
- [MIPS] Fix lowering of irregular vector arguments · cc999c95
  LemonBoy authored Mar 11, 2021
  cc999c95
- [RISCV] Support fixed vector copysign. · c82f4429
  Craig Topper authored Mar 11, 2021
  c82f4429
- [ARM] Move t2DoLoopStart reg alloc hint · bd516d24
  David Green authored Mar 11, 2021
  bd516d24
- [ARM] Improve WLS lowering · fad70c30
  David Green authored Mar 11, 2021
  fad70c30
- [RISCV] Handle vmv.x.s intrinsic for i64 vectors on RV32. · 0dff8a96
  Craig Topper authored Mar 11, 2021
  0dff8a96
- [RISCV] Support extract_vector_elt for fixed and scalable masked registers. · 9c841cb8
  Craig Topper authored Mar 11, 2021
  9c841cb8
- [ValueTypes][RISCV] Add MVT for v1f16. · e9426dfb
  Craig Topper authored Mar 11, 2021
  e9426dfb
- AMDGPU/GlobalISel: Improve private addressing mode matching · 70cb57d7
  Matt Arsenault authored Mar 04, 2021
  70cb57d7
- GlobalISel: Fix off by one in finding explicit byval alignment · cf5ecd56
  Matt Arsenault authored Mar 06, 2021
  cf5ecd56
- AMDGPU/GlobalISel: Add more tests for byval arguments · 0e0c7ef8
  Matt Arsenault authored Mar 06, 2021
  
  0e0c7ef8
- [PowerPC] Exploit paddi instruction on Power 10 for constant materialization · e021de0a
  Stefan Pintilie authored Mar 11, 2021
  e021de0a
- [PowerPC] Fix multi-use case for swap reduction · 72c4cbd6
  Qiu Chaofan authored Mar 11, 2021
  72c4cbd6
- [AArch64][SVE] Add fixed/scalable lowering of FMAXIMUM/FMINIMUM ISD nodes · 860ae9d5
  Bradley Smith authored Mar 10, 2021
  860ae9d5
- Revert "[AArch64][SVE] Allow accesses to SVE stack objects to use frame pointer" · ea834c83
  Bradley Smith authored Mar 10, 2021
  ea834c83
- [PowerPC] Fix infinite loop in peephole CR optimization (PR49509) · 2489cbaa
  Nikita Popov authored Mar 10, 2021
  2489cbaa
- Revert rGcd938ab162b0ac560dd0e9fee290980c7e0e47e5 "[X86]... · bc5e9ec2
  Simon Pilgrim authored Mar 11, 2021
  bc5e9ec2
- [X86] Don't attempt to fold sub(C1, xor(X, C2)) with opaque constants · 77394c12
  Simon Pilgrim authored Mar 11, 2021
  77394c12
- [Statepoint Lowering] Handle the case with several gc.result · 04809277
  Serguei Katkov authored Mar 11, 2021
  04809277
- [RISCV] Merge fixed-vectors-int-splat-rv32.ll and fixed-vectors-int-splat-rv64.ll. · 47c7a6cf
  Craig Topper authored Mar 10, 2021
  47c7a6cf
- [RISCV] Add v2i64 _vi_ and _iv_ test cases to fixed-vectors-int.ll since we no longer crash. · 85ae96d8
  Craig Topper authored Mar 10, 2021
  85ae96d8
- Revert "WIP" · 9c3eb457
  David Blaikie authored Mar 10, 2021
  9c3eb457
- WIP · 60238f29
  David Blaikie authored Mar 10, 2021
  
  60238f29
- [AMDGPU] Always create Stack Object for reserved VGPR · 66340846
  Ruiling Song authored Mar 10, 2021
  66340846
- [mir] Change 'undef' for MMO base addresses to 'unknown-address' · 134a179d
  Daniel Sanders authored Mar 05, 2021
  134a179d
Mar 10, 2021
- [AArch64] Extend vecreduce -> udot handling to mla reductions · 1a808286
  David Green authored Mar 10, 2021
  1a808286
- [AArch64] Extend vecreduce -> udot handling to v8i8 · a02f5068
  David Green authored Mar 10, 2021
  a02f5068
- [AMDGPU] Always expand system scope fp atomics on gfx90a · 574a9dab
  Stanislav Mekhanoshin authored Mar 05, 2021
  574a9dab
- [PowerPC] Implement patterns for PC-Rel zextload/extload byte loads · 8b540c54
  Amy Kwan authored Mar 04, 2021
  8b540c54
- [RISCV] Starting fixing issues that prevent us from testing vXi64 intrinsics on RV32. · 0c73a506
  Craig Topper authored Mar 10, 2021
  0c73a506
- [RISCV] Manually split vector operands to VECREDUCE when handling vXi64 vectors on RV32. · 1e391186
  Craig Topper authored Mar 10, 2021
  1e391186