Commits · 7b789562244ee941b7bf2cefeb3fc08a59a01865 · Roger Ferrer / llvm-epi · GitLab

Jul 21, 2021
- [AArch64][GlobalISel] Widen s2 and s4 G_IMPLICIT_DEF + G_FREEZE · d0af732b
  Jessica Paquette authored Jul 20, 2021
  d0af732b
- [AArch64] Regenerate and add more tests for i128 atomics. · 301b21a9
  Eli Friedman authored Jul 21, 2021
  301b21a9
- AArch64: support 8 & 16-bit atomic operations in GlobalISel · 291e0daa
  Tim Northover authored Jul 21, 2021
  291e0daa
- [GlobalISel] Tail call memcpy/memmove/memset even in the presence of copies · a14b4e34
  Jon Roelofs authored Jul 06, 2021
  a14b4e34
- [GlobalISel] Mark memcpy/memmove/memset as thisreturn · afaf9282
  Jon Roelofs authored Jul 02, 2021
  afaf9282
- [AArch64][GlobalISel] Legalize ctpop for v2s64, v2s32, v4s32, v4s16, v8s16 · 75187aa3
  Jon Roelofs authored Jul 20, 2021
  75187aa3
Jul 20, 2021
- [AArch64] Add tests for 128-bit atomic loads with casp available. · c4e1acf1
  Eli Friedman authored Jul 20, 2021
  c4e1acf1
- [AArch64][GlobalISel] Select llvm.aarch64.neon.st2 intrinsics · 8f54ebd5
  Jessica Paquette authored Jul 19, 2021
  8f54ebd5
- [AArch64] Use the CMP_SWAP_128 variants added in 843c6140 . · 664a1fd9
  Eli Friedman authored Jul 20, 2021
  664a1fd9
- [AArch64] Fix i128 cmpxchg using ldxp/stxp. · 843c6140
  Eli Friedman authored Jul 20, 2021
  843c6140
- [AArch64][SVE] Move instcombine like transforms out of SVEIntrinsicOpts · 191f9fa5
  Bradley Smith authored Jul 13, 2021
  191f9fa5
- [AArch64] Regenerate some tests checks. NFC · ee072e20
  David Green authored Jul 20, 2021
  
  ee072e20
- [AArch64][GlobalISel] Don't form truncstores in postlegalizer-lowering for s128. · 56a6686e
  Amara Emerson authored Jul 20, 2021
  56a6686e
- AArch64/GlobalISel: Preserve memory types · 30fa074c
  Matt Arsenault authored Jul 16, 2021
  
  30fa074c
Jul 19, 2021
- Revert "[llvm][sve] Lowering for VLS truncating stores" because it · fd972bb9
  Amy Huang authored Jul 19, 2021
  fd972bb9
- [GlobalISel] Fix load-or combine moving loads across potential aliasing stores. · 03cdb522
  Amara Emerson authored Jul 18, 2021
  03cdb522
- [AArch64][SVE] Optimize bitcasts between unpacked half/i16 vectors. · 0ed05735
  Sander de Smalen authored Jul 19, 2021
  0ed05735
Jul 18, 2021
- [AArch64][GlobalISel] Legalize bswap <2 x i16> · 5cd63e9e
  Jon Roelofs authored Jul 09, 2021
  5cd63e9e
Jul 17, 2021
- [AArch64] Prepare for changes to STEP_VECTOR. · e41e865b
  Eli Friedman authored Jul 12, 2021
  e41e865b
Jul 16, 2021
- [GlobalISel] Fix non-pow-2 legalization of s56 stores. · 9637848f
  Amara Emerson authored Jul 16, 2021
  9637848f
- GlobalISel: Preserve memory type for memset expansion · 5a0d940f
  Matt Arsenault authored Jul 16, 2021
  
  5a0d940f
- AArch64/GlobalISel: Update tests to use correct memory types · e0a080d3
  Matt Arsenault authored Jul 16, 2021
  
  e0a080d3
- [AArch64][SME] Add load and store instructions · 99eb96f0
  Cullen Rhodes authored Jul 16, 2021
  99eb96f0
Jul 15, 2021
- [AArch64][GlobalISel] Clamp <n x p0> vecs when legalizing G_EXTRACT_VECTOR_ELT · 46c8e712
  Jessica Paquette authored Jul 13, 2021
  46c8e712
- [test] Avoid llvm-readelf/llvm-readobj one-dash long options and deprecated... · aa3df8dd
  Fangrui Song authored Jul 15, 2021
  aa3df8dd
- [GlobalISel] Fix infinite loop in reassociationCanBreakAddressingModePattern · 5da0f9ab
  Jessica Paquette authored Jul 15, 2021
  5da0f9ab
- [AArch64][GlobalISel] Optimise lowering for some vector types for min/max · 831ee6b0
  Irina Dobrescu authored Jul 09, 2021
  831ee6b0
Jul 14, 2021
- [AArch64] Fix selection of G_UNMERGE <2 x s16> · 0e49c54a
  Jon Roelofs authored Jul 14, 2021
  0e49c54a
- [RemoveRedundantDebugValues] Add a Pass that removes redundant DBG_VALUEs · df686842
  Djordje Todorovic authored Jun 28, 2021
  df686842
- [DebugInfo] Correctly update dbg.values with duplicated location ops · 810e4c3c
  Stephen Tozer authored Jul 13, 2021
  810e4c3c
- [AArch64][GlobalISel] Mark v2s64 -> v2p0 G_INTTOPTR as legal · 5bd7cc4f
  Jessica Paquette authored Jul 13, 2021
  5bd7cc4f
Jul 13, 2021
- [Tests] Fix test broken by: 43c7ca8e [AArch64][GlobalISel] Legalize store <2 x i16> · 3e5cff19
  Jon Roelofs authored Jul 13, 2021
  
  3e5cff19
- [AArch64][GlobalISel] Legalize load <2 x i16> · eba638db
  Jon Roelofs authored Jul 09, 2021
  eba638db
- [AArch64][GlobalISel] Legalize store <2 x i16> · 43c7ca8e
  Jon Roelofs authored Jul 09, 2021
  43c7ca8e
- AArch64: use 4-byte slots for arm64_32 pointers in a tail call · 7802f62b
  Tim Northover authored Jun 28, 2021
  
  7802f62b
- [GlobalISel] Handle more types in narrowScalar for eq/ne G_ICMP · 47d0780f
  Jessica Paquette authored Jun 29, 2021
  47d0780f
- [AArch64] Optimize overflow checks for [s|u]mul.with.overflow.i32. · 6c04b7dd
  Eli Friedman authored Jul 12, 2021
  6c04b7dd
Jul 12, 2021
- [SelectionDAG] Simplify PromoteIntRes_INSERT_SUBVECTOR to only handle result · 112c0903
  Bradley Smith authored Jul 08, 2021
  112c0903
- [llvm][sve] Lowering for VLS truncating stores · c305557a
  David Truby authored Jul 12, 2021
  c305557a
Jul 10, 2021
- [AArch64][GlobalISel] Implement moreElements legalization for G_SHUFFLE_VECTOR. · 97c42639
  Amara Emerson authored Jul 09, 2021
  97c42639