Summary:
Some changes are made to cmake, especially the addition of a new
LLVM_ENABLE_PROJECTS option that makes the build system aware of
the monorepo directory structure.

Also a new script is added in llvm/utils/git-svn/. When present in
the $PATH, it enables a `git llvm` command. It is providing at this
point only the ability to push from the git monorepo: `git llvm push`.
It is intended to evolves with more features, for instance I plan on
features like `git llvm show r284955` to help working with sequential
revision numbers.
The push feature is taken from Justin Lebar's script available here:
https://github.com/jlebar/llvm-repo-tools/

Reviewers: jlebar

Subscribers: mgorny, modocache, llvm-commits

Differential Revision: https://reviews.llvm.org/D26334

llvm-svn: 286123

llvm-svn: 286120

Differential Revision: https://reviews.llvm.org/D26292

llvm-svn: 286119

Separate the subregister splitting logic to re-use later.

llvm-svn: 286118

llvm-svn: 286117

This was reverted at r285866 because there was a crash handling a scalar
select of vectors. I added a check for that pattern and a test case based
on the example provided in the post-commit thread for r285732.

llvm-svn: 286113

* Use a generic vector unit to model the issue unit more accurately.
* Update some vector instructions that actually use the vector unit for more
  than one cycle.

Review: Ulrich Weigand
llvm-svn: 286112

This patch adds support for 16 bit floating point registers to the inline asm register selection on AArch64.

Without this patch, register allocation for the example below fails.

define half @test(half %a1, half %a2) #0 {
entry:
  %0 = tail call half asm "sqrshl ${0:h}, ${1:h}, ${2:h}", "=w,w,w" (half %a1, half %a2) #1
  ret half %0
}

Patch by Florian Hahn.

Differential Revision: https://reviews.llvm.org/D25080

llvm-svn: 286111

This feature has been disabled for some time now, so remove cruft.

Differential Revision: https://reviews.llvm.org/D26248

llvm-svn: 286110

IssueWidth updated to reflect the capacity of the issue unit correctly.
Correct number of FX and LS units modelled (2, was 1).

Review: Ulrich Weigand
llvm-svn: 286109

Differential Revision: https://reviews.llvm.org/D26252

llvm-svn: 286108

When the base register (register pointing to the jump table) is the PC, we expect the jump table to directly follow the jump sequence with no intervening padding.

If there is intervening padding, the calculated offsets will not be correct. One solution would be to account for any padding in the emitted LDRB instruction, but at the moment we don't support emitting MCExprs for the load offset.

In the meantime, it's correct and only a slight amount worse to just move the padding up, from just before the jump table to just before the jump instruction sequence. We can do that by emitting code alignment before the jump sequence, as we know the number of instructions in the sequence is always 4.

llvm-svn: 286107

llvm-svn: 286105

cpu/triple duplication

llvm-svn: 286104

llvm-svn: 286095

Summary: Update the docs to match the changes in http://reviews.llvm.org/D7132

Reviewers: beanz, llvm-commits, modocache

Differential Revision: https://reviews.llvm.org/D26296

llvm-svn: 286094

[AVX-512] Remove masked pmovzx/pmovsx builtins and autoupgrade them to selects and native zext/sext.

This mostly reuses earlier autoupgrade support for the sse and avx equivalents. Just needed to add the code to add the select.

llvm-svn: 286092

[X86] Remove GCCBuiltins from cvtsi2ss/cvtsi2sd/cvtss2sd intrinsics as they aren't used by clang. Add TODOs to remove these and some other unused intrinsics.

llvm-svn: 286091

llvm-svn: 286090

[AVX-512] Remove 128/256 masked pshufb intrinsics. Autoupgrade them to legacy intrinsics and a select.

llvm-svn: 286089

Also delete a comment I forgot to delete.

llvm-svn: 286087

llvm-svn: 286086

llvm-svn: 286085

Cmake has not recognized that Hexagon.td has a new dependency in
HexagonPatterns.td. All changes to that file were not visible to
the build bots.

llvm-svn: 286084

llvm-svn: 286083

This handles the last case of the builtin function calls that we would
generate code which differed from Microsoft's ABI.  Rather than
generating a call to `__pow{d,s}i2` we now promote the parameter to a
float or double and invoke `powf` or `pow` instead.

Addresses PR30825!

llvm-svn: 286082

llvm-svn: 286081

The clr/set/toggle-bit instructions (with the bit index given as an
immediate operand) had both, custom selection code that generated them,
and selection patterns at the same time. The selection patterns were
not used, because the custom selection code was executed first.
This patch removes the custom code in favor of the selection patterns.
The custom code handled 64-bit registers as well with an immediate bit
index, and so new patterns were added to implement that.

It was also the same case for the instruction "Rd += asr(Rs, Rt)",
except that the custom code did not offer any additional functionality,
and was simply removed.

llvm-svn: 286080

Remove unnecessary type casts in patterns.

llvm-svn: 286079

Give simpler or more meaningful names to pat frags and xforms.

llvm-svn: 286078

Remove unnecessary C++ functions for SDNode transforms. Move more
pat frags to files where they are used.

llvm-svn: 286077

Add pat frags for any-, sign-, and zero-extensions.

llvm-svn: 286076

llvm-svn: 286075

In preparation for demandedelts support

llvm-svn: 286074

[AVX-512] Remove intrinsics for 128/256-bit masked variable shift. Instead upgrade them to a select and the older AVX2 intrinsic.

llvm-svn: 286073

[AVX-512] Remove intrinsics for 128/256-bit masked shift by immediate. Instead upgrade them to a select and the older SSE/AVX2 intrinsic.

llvm-svn: 286072

llvm-svn: 286071

[AVX-512] Remove intrinsics for 128/256-bit masked shift by single element in xmm. Instead upgrade them to a select and the older SSE/AVX2 intrinsic.

llvm-svn: 286070

[AVX-512] Remove a 512-bit test cases from the avx512vl test file. It already exists in the avx512f test file.

llvm-svn: 286069

In preparation for demandedelts support

llvm-svn: 286068