Commits · 98b71c53517f89017c765ac73259cb136f5e4955 · Roger Ferrer / llvm-epi · GitLab

Feb 03, 2021
- [Statepoint] Handle 'undef' operand tied to def · de305b04
  Serguei Katkov authored Feb 02, 2021
  de305b04
- [yaml2obj][wasm] Support numeric relocation type · fb7c3663
  Fangrui Song authored Feb 02, 2021
  fb7c3663
- [PowerPC] [NFC] fix wording typos · b0869a7d
  Chen Zheng authored Feb 02, 2021
  b0869a7d
- AMDGPU: Fix adding extra operands for i128 asm constraints · af2cbe8e
  Matt Arsenault authored Feb 02, 2021
  af2cbe8e
- AMDGPU: Don't consider global pressure when bundling soft clauses · 1e377a27
  Matt Arsenault authored Jan 30, 2021
  1e377a27
- [GlobalISel] Check if branches use the same MBB in matchOptBrCondByInvertingCond · 02d4b365
  Jessica Paquette authored Feb 02, 2021
  02d4b365
Feb 02, 2021
- [AArch64] Homogeneous Prolog and Epilog Size Optimization · 4f58b1bd
  Kyungwoo Lee authored Feb 01, 2021
  4f58b1bd
- Diagnose if a SLEB128 is too large to fit in an int64_t. · 32e98f05
  Richard Smith authored Jan 26, 2021
  32e98f05
- [ConstraintElimination] Skip pointer casts. · d8e90716
  Florian Hahn authored Feb 02, 2021
  d8e90716
- [CSSPGO] Introducing distribution factor for pseudo probe. · 3d89b3cb
  Hongtao Yu authored Dec 11, 2020
  3d89b3cb
- [RISCV] Fix incorrect RVV sdiv/udiv lowering · b4106f9c
  Fraser Cormack authored Feb 02, 2021
  b4106f9c
- [RISCV] Correct types in tablegen multiclasses found by D95874. · c4fd1981
  Craig Topper authored Feb 02, 2021
  
  c4fd1981
- [ConstraintElimination] Fix -Wunused-function in -DLLVM_ENABLE_ASSERTIONS=off build · 51da1268
  Fangrui Song authored Feb 02, 2021
  
  51da1268
- [RISCV] Use a ComplexPattern to merge isel patterns for vector load/store with... · 912306ef
  Craig Topper authored Feb 02, 2021
  912306ef
- [MC] Upgrade DWARF version to 5 upon .file 0 · 3e8ab54b
  Fangrui Song authored Feb 02, 2021
  3e8ab54b
- [MC] Support SHF_GNU_RETAIN as section flag 'R' · 1477ed84
  Fangrui Song authored Feb 02, 2021
  1477ed84
- [yaml2obj/obj2yaml/llvm-readobj] Support SHF_GNU_RETAIN · 1560a000
  Fangrui Song authored Feb 02, 2021
  1560a000
- [InlineFunction] Only update noalias scopes once for an instruction. · 50c523a9
  Jeroen Dobbelaere authored Feb 02, 2021
  50c523a9
- [ARM] Correct some tablegen operand types. NFC · 3e780616
  David Green authored Feb 02, 2021
  
  3e780616
- [ConstraintElimination] Add nicer way to dump constraints (NFC). · 3e09bc25
  Florian Hahn authored Feb 02, 2021
  3e09bc25
- [ARM] Mark MVE_VMOV_to_lane_32 as isInsertSubregLike · 2753722b
  David Green authored Feb 02, 2021
  2753722b
- [AMDGPU] Remove unused tmp register · 8b898b19
  Sebastian Neubauer authored Feb 02, 2021
  8b898b19
- [AMDGPU] Save fp/bp after csr saves · 6b6ae583
  Sebastian Neubauer authored Feb 01, 2021
  6b6ae583
- [CSSPGO] Factor out common part for CSSPGO inline and AFDO inline · 1645f465
  Wenlei He authored Jan 19, 2021
  1645f465
- [PowerPC] Materialize 34 bit constants with pli on Power 10. · 288f762b
  Stefan Pintilie authored Feb 02, 2021
  288f762b
- [ARM] Add MVE insert-of-extract pattern · 3a5adf84
  David Green authored Feb 02, 2021
  3a5adf84
- [InstCombine] Host inversion out of ashr's value operand (PR48995) · 485c4b55
  Roman Lebedev authored Feb 02, 2021
  485c4b55
- Revert "[InstrProfiling] Use !associated metadata for counters, data and values" · 4f1320b7
  Tom Weaver authored Feb 02, 2021
  4f1320b7
- [ARM] Select VINS from vector inserts · c7225756
  David Green authored Feb 02, 2021
  c7225756
- [X86][SSE] LowerINSERT_VECTOR_ELT - pull out repeated EltSizeInBits calls. NFCI. · 8c2e075c
  Simon Pilgrim authored Feb 02, 2021
  
  8c2e075c
- NFC: Migrate SpeculateAroundPHIs to work on InstructionCost · 3d3ca8f8
  Sander de Smalen authored Feb 02, 2021
  3d3ca8f8
- NFC: Migrate SimpleLoopUnswitch to work on InstructionCost · 00da3227
  Sander de Smalen authored Feb 02, 2021
  00da3227
- [AMDGPU][MC] Corrected parsing of optional modifiers · 586df384
  Dmitry Preobrazhensky authored Feb 02, 2021
  586df384
- [X86][AVX512] Support variable-index vector insertion on AVX512 targets (PR47924) · d46a6b3d
  Simon Pilgrim authored Feb 02, 2021
  d46a6b3d
- [X86] Fix disassembly of x86-64 GDTLS code sequence · 94fedd26
  Andrew Ng authored Jan 27, 2021
  94fedd26
- [X86][AVX] Add missing VEX_WIG tags from... · 4d904776
  Simon Pilgrim authored Feb 02, 2021
  4d904776
- [ARM] Remove DLS lr, lr · 48230355
  David Green authored Feb 02, 2021
  48230355
- Revert "[CSSPGO] Factor out common part for CSSPGO inline and AFDO inline" · 48ca6da9
  Adrian Kuegel authored Feb 02, 2021
  48ca6da9
- Revert "Fix build break from D95024" · 3a65ec4b
  Adrian Kuegel authored Feb 02, 2021
  3a65ec4b
- [SVE][LoopVectorize] Add masked load/store and gather/scatter support for SVE · d4d4ceeb
  David Sherwood authored Jan 22, 2021
  d4d4ceeb