Commits · cb261e30fbb174085d2eea4f4afc3cef2838b7f7 · Roger Ferrer / llvm-epi · GitLab

Nov 22, 2022
- [AArch64][clang] implement 2022 General Data-Processing instructions · cb261e30
  Ties Stuij authored Nov 22, 2022
  cb261e30
- [AMDGPU] Add encoding tests for SALU_CYCLE_2/3 · de767db6
  Piotr Sobczak authored Nov 22, 2022
  de767db6
- [RISCV] Add CodeGen support and MC testcase of RISCV Zca Extension · 219417b2
  WuXinlong authored Nov 21, 2022
  219417b2
Nov 21, 2022
- [WebAssembly] Update relaxed-simd instruction names · ae96b5bd
  Thomas Lively authored Nov 21, 2022
  ae96b5bd
- [PowerPC] Add new load/store with length instructions to Future CPU. · bd680704
  Maryam Moghadas authored Oct 28, 2022
  bd680704
- [AArch64][NFC] SME2 Add missing tests for usvdot and sumlall instructions · c0414518
  Caroline Concatto authored Nov 21, 2022
  
  c0414518
- [LoongArch] AsmParser support for the li.[wd] pseudo instructions · f873c50c
  wanglei authored Nov 21, 2022
  f873c50c
- [LoongArch] Support parsing la* pseudo instructions · a7ec7f6d
  wanglei authored Nov 21, 2022
  a7ec7f6d
Nov 18, 2022
- [LoongArch] Implement assembler branches pseudo instructions · bfa3551d
  wanglei authored Nov 18, 2022
  bfa3551d
Nov 16, 2022
- [AMDGPU][GFX11] Refactor VOPD operands handling · e468b1b7
  Dmitry Preobrazhensky authored Nov 16, 2022
  e468b1b7
- [MC][LoongArch] Fix needsRelocateWithSymbol() implementation · b18cdeac
  Youling Tang authored Nov 16, 2022
  b18cdeac
Nov 14, 2022
- [AMDGPU][MC][NFC] Rename VOP3 VOPC test files · 38f47d90
  Joe Nash authored Nov 14, 2022
  38f47d90
- [RISCV] Implement assembler support for XVentanaCondOps · 780c5398
  Philip Reames authored Nov 14, 2022
  780c5398
- [AMDGPU][AsmParser] Forbid TFE modifiers for MBUF stores. · d55594bb
  Ivan Kosarev authored Nov 14, 2022
  d55594bb
- [AMDGPU][MC] Support TFE modifiers in MUBUF loads and stores. · 1b560e6a
  Ivan Kosarev authored Nov 14, 2022
  1b560e6a
- [AArch64] Add all SME2.1 instructions Assembly/Disassembly · 3eacda45
  Caroline Concatto authored Nov 03, 2022
  3eacda45
- [AMDGPU][MC][GFX11] Improve diagnostic messages for invalid VOPD syntax · ef6f3c76
  Dmitry Preobrazhensky authored Nov 14, 2022
  ef6f3c76
Nov 12, 2022
- [LoongArch] Implement MCTargetExpr::fixELFSymbolsInTLSFixups hook · 39b1fec1
  wanglei authored Nov 12, 2022
  39b1fec1
Nov 11, 2022
- [AMDGPU][MC] Disable SGPRs as src operands of VOP3 VINTRP instructions · 05baf681
  Dmitry Preobrazhensky authored Nov 11, 2022
  05baf681
Nov 10, 2022
- [AArch64]SME2 Multi vector Sel Load and Store instructions · ecab1bc0
  Caroline Concatto authored Nov 02, 2022
  ecab1bc0
- [PowerPC] Add the SUBFUS instruction to Future CPU. · 1ef2a92d
  Stefan Pintilie authored Nov 09, 2022
  1ef2a92d
- [AArch64] RME MEC instructions and system registers · 00d98e65
  Keith Walker authored Nov 04, 2022
  00d98e65
- [AsmParser] Match mandatory operands following optional operands. · af6b1f79
  Ivan Kosarev authored Nov 10, 2022
  af6b1f79
- [AArch64][SVE2] Add the SVE2.1 permute vector elements (quadword) instructions · 098e2013
  David Sherwood authored Nov 07, 2022
  098e2013
- [AArch64][SVE2] Add the SVE2.1 tbxq instruction · e3fef88a
  David Sherwood authored Nov 08, 2022
  e3fef88a
Nov 09, 2022
- [AArch64][SVE2] Add the SVE2.1 integer quadword reduction instructions · 835de8dc
  David Sherwood authored Nov 03, 2022
  835de8dc
- [M68k] Add support for atomic instructions · e086b24d
  Sheng authored Nov 09, 2022
  e086b24d
- [AArch64][SVE2] Add the SVE2.1 quadword structured load/store instructions · 78f11a39
  David Sherwood authored Nov 07, 2022
  78f11a39
Nov 08, 2022
- [AArch64][SVE2] Add the SVE2.1 pmov instructions · b048b1b7
  David Sherwood authored Nov 07, 2022
  b048b1b7
- [AArch64]SME2 Single and Multi vector Shift and Multiply instructions · d917276c
  Caroline Concatto authored Nov 08, 2022
  d917276c
- [AArch64][SVE2] Add the SVE2.1 dupq and extq instructions · 8f60eee9
  David Sherwood authored Nov 07, 2022
  8f60eee9
- [AArch64]SME2 MOV Instructions · 1a917568
  Caroline Concatto authored Nov 02, 2022
  1a917568
- [AArch64][SVE2] Add the SVE2.1 FP quadword reduction instructions · 17813095
  David Sherwood authored Nov 03, 2022
  17813095
Nov 07, 2022
- [AArch64][SVE2] Add the SVE2.1 quadword variants of ld1w/ld1d/st1w/st1d · a9d7b18b
  David Sherwood authored Nov 01, 2022
  a9d7b18b
- [AArch64][SVE2] Add the SVE2.1 BF16 instructions · cf69895a
  David Sherwood authored Nov 02, 2022
  cf69895a
- [AArch64] Add SME2.1 target feature for Armv9-A 2022 Architecture Extension · 12a6572d
  David Sherwood authored Nov 03, 2022
  12a6572d
- [AMDGPU][MC][GFX11][NFC] Correct VINTERP src operands · 8f689521
  Dmitry Preobrazhensky authored Nov 07, 2022
  8f689521
- [AMDGPU][MC][GFX10+] Enable literal operands with permlane16/permlanex16 · 6e279f5b
  Dmitry Preobrazhensky authored Nov 07, 2022
  6e279f5b
Nov 05, 2022
- Change a 'default_triple' to 'object-emission' · 38c07d90
  Paul Robinson authored Nov 05, 2022
  38c07d90
Nov 04, 2022
- [Test] Fix CHECK typo. · a7fa5feb
  Zequan Wu authored Nov 02, 2022
  a7fa5feb