Commits · cfeecdf7b6df9cd89488948b440f8deeb458104c · Roger Ferrer / llvm-epi · GitLab

Jan 07, 2021
- [llvm] Use llvm::all_of (NFC) · cfeecdf7
  Kazu Hirata authored Jan 06, 2021
  
  cfeecdf7
- [llvm] Use BasicBlock::phis() (NFC) · 9b228f10
  Kazu Hirata authored Jan 06, 2021
  
  9b228f10
- [RISCV] Fix a few section number comments in RISCVInstrInfoVPseudos.td to... · 7a8ced43
  Craig Topper authored Jan 06, 2021
  7a8ced43
- [PPC] Remove old PPCSubTarget variable. · 4bdab548
  Kit Barton authored Jan 06, 2021
  4bdab548
Jan 06, 2021
- [RISCV] Return a vXi1 vector type from getSetCCResultType if V extension is enabled. · c68faed0
  Craig Topper authored Jan 06, 2021
  c68faed0
- [X86] Remove [ER]SP from all CSR lists · 08e5e91e
  Reid Kleckner authored Jan 05, 2021
  08e5e91e
- AMDGPU/GlobalISel: Update fdiv lowering for denormal/ulp interaction · ab3a3f54
  Matt Arsenault authored Jan 05, 2021
  ab3a3f54
- [AArch64] Rearrange mul(dup(sext/zext)) to mul(sext/zext(dup)) · 350247a9
  Nicholas Guy authored Dec 02, 2020
  350247a9
- [Hexagon] Wrap functions only used in asserts in ifndef NDEBUG · 46975b5b
  Krzysztof Parzyszek authored Jan 06, 2021
  
  46975b5b
- [MIPS] MipsAsmParser - Pass Twine by const reference instead of by value. NFCI. · df5c2caf
  Simon Pilgrim authored Jan 06, 2021
  
  df5c2caf
- [AArch64] Add BRB IALL and BRB INJ instructions · 643e3c90
  Tomas Matheson authored Dec 29, 2020
  643e3c90
- [PowerPC] Fix issue where vsrq is given incorrect shift vector · cb0c034e
  Stefan Pintilie authored Jan 05, 2021
  cb0c034e
- [ARM] Handle any extend whilst lowering addw/addl/subw/subl · 63dce70b
  David Green authored Jan 06, 2021
  63dce70b
- [ARM] Handle any extend whilst lowering mull · ddb82fc7
  David Green authored Jan 06, 2021
  ddb82fc7
- [AArch64] Handle any extend whilst lowering addw/addl/subw/subl · a9b6440e
  David Green authored Jan 06, 2021
  a9b6440e
- [AArch64] Handle any extend whilst lowering mull · 78d8a821
  David Green authored Jan 06, 2021
  78d8a821
- [AArch64][SVE] Emit DWARF location expression for SVE stack objects. · a7e3339f
  Sander de Smalen authored Jan 06, 2021
  a7e3339f
- [AArch64] Use faddp to implement fadd reductions. · a9f5e437
  Sander de Smalen authored Jan 05, 2021
  a9f5e437
- [RISCV] Add vector integer mul/mulh/div/rem ISel patterns · e130dea9
  Fraser Cormack authored Jan 04, 2021
  e130dea9
- [llvm] Use llvm::lower_bound and llvm::upper_bound (NFC) · cd088ba7
  Kazu Hirata authored Jan 05, 2021
  
  cd088ba7
- [GlobalISel] Base implementation for sret demotion. · d68458bd
  Christudasan Devadasan authored Dec 23, 2020
  d68458bd
- [X86] Update X86InstCombineIntrinsic to use CreateShuffleVector with one vector · 8444a249
  Juneyoung Lee authored Jan 05, 2021
  8444a249
Jan 05, 2021
- AMDGPU: Annotate amdgpu.noclobber for global loads only · cb5b52a0
  Changpeng Fang authored Jan 05, 2021
  cb5b52a0
- [Hexagon] Silence unused function warning with gcc10, NFC · ee11bf31
  Krzysztof Parzyszek authored Jan 05, 2021
  
  ee11bf31
- [RISCV] Move shift ComplexPatterns and custom isel to PatFrags with predicates · 7b5a0e2f
  Craig Topper authored Jan 05, 2021
  7b5a0e2f
- [WebAssembly] Prototype prefetch instructions · 497026c9
  Thomas Lively authored Jan 05, 2021
  497026c9
- [NFC] Rename registerAliasAnalyses -> registerDefaultAliasAnalyses · 28a326eb
  Arthur Eubanks authored Jan 02, 2021
  28a326eb
- [RISCV] Don't parse 'vmsltu.vi v0, v1, 0' as 'vmsleu.vi v0, v1, -1' · 210bc3dc
  Craig Topper authored Jan 05, 2021
  210bc3dc
- [RISCV] Don't print zext.b alias. · 249d7de1
  Craig Topper authored Jan 05, 2021
  249d7de1
- [RISCV] Match vmslt(u).vx intrinsics with a small immediate to vmsle(u).vx. · c707716c
  Craig Topper authored Jan 05, 2021
  c707716c
- [AMDGPU] Remove deprecated V_MUL_LO_I32 from GFX10 · 60466fad
  Joe Nash authored Jan 04, 2021
  60466fad
- [AArch64][SVE] Add optimization to remove redundant ptest instructions · c73ae747
  Bradley Smith authored Dec 14, 2020
  c73ae747
- [X86][AVX] combineVectorSignBitsTruncation - use PACKSS/PACKUS in more AVX cases · 73a44f43
  Simon Pilgrim authored Jan 05, 2021
  73a44f43
- [X86] getMemoryOpCost - use dyn_cast_or_null<StoreInst>. NFCI. · dc74d7ed
  Simon Pilgrim authored Jan 05, 2021
  dc74d7ed
- [AMDGPU] Handle v_fmac_legacy_f32 in SIFoldOperands · 3914bebe
  Jay Foad authored Jan 04, 2021
  3914bebe
- [AMDGPU] Split out new helper function macToMad in SIFoldOperands. NFC. · 4e6054a8
  Jay Foad authored Jan 04, 2021
  4e6054a8
- [VE] Support SJLJ exception related instructions · f784be07
  Kazushi (Jam) Marukawa authored Dec 15, 2020
  f784be07
- [SVE] Lower vector CTLZ, CTPOP and CTTZ operations. · eba6deab
  Paul Walker authored Dec 18, 2020
  eba6deab
- [WebAssembly] call_indirect causes indirect function table import · 9ad83fd6
  Andy Wingo authored Dec 08, 2020
  9ad83fd6
- [VE][NFC] Fix typo in comments · 53a341a6
  Kazushi (Jam) Marukawa authored Jan 05, 2021
  
  53a341a6