Commits · d1b58cada61aa8bc44d8e8ef9c23ed12ef7b549b · Roger Ferrer / llvm-epi · GitLab

Jul 19, 2022
- [llvm-objdump] Support --symbolize-operands when there is a single... · ed93d157
  Rahman Lavaee authored Jul 16, 2022
  ed93d157
Jul 18, 2022
- CodeGen: Remove AliasAnalysis from regalloc · 8d0383eb
  Matt Arsenault authored Jun 24, 2022
  8d0383eb
- [AMDGPU] Support for gfx940 fp8 smfmac · 523a99c0
  Stanislav Mekhanoshin authored Jul 15, 2022
  523a99c0
- [AMDGPU] Support for gfx940 fp8 mfma · 2695f0a6
  Stanislav Mekhanoshin authored Jul 15, 2022
  2695f0a6
- [AMDGPU] Support for gfx940 fp8 conversions · 9fa5a6b7
  Stanislav Mekhanoshin authored Jul 15, 2022
  9fa5a6b7
- [LiveIntervals] Find better anchoring end points when repairing ranges · dbed4326
  Jay Foad authored Jul 18, 2022
  dbed4326
- Reland "[SystemZ][z/OS] Fix f32 variadic argument assertion" · c444f037
  Mubariz Afzal authored Jul 18, 2022
  c444f037
- [RISCV] Optimize (seteq (i64 (and X, 0xffffffff)), C1) · 0b027528
  Craig Topper authored Jul 18, 2022
  0b027528
- [RISCV] Pre-commit tests for D129980. NFC · 464b3a9d
  Craig Topper authored Jul 18, 2022
  464b3a9d
- [coro async] Fix code to run coro.async.end cleanup like the legacy pass did · 28ebd13d
  Arnold Schwaighofer authored Jul 15, 2022
  28ebd13d
- llvm-reduce: Add reduction for instruction defs · e24b390d
  Matt Arsenault authored Jun 27, 2022
  e24b390d
- llvm-reduce: Add reduction for custom register masks · 0f9d9edd
  Matt Arsenault authored Jun 22, 2022
  0f9d9edd
- Reapply "[NVPTX] Use the mask() operator to initialize packed structs with pointers" · 32eed882
  Igor Kudrin authored Jul 18, 2022
  32eed882
- [RISCV] Add isel patterns for ineg+setge/le/uge/ule. · 7c0b9b37
  Craig Topper authored Jul 18, 2022
  7c0b9b37
- [IR] Allow absence for Min module flags and make AArch64 BTI/PAC-RET flags backward compatible · b3fd3a9a
  Fangrui Song authored Jul 18, 2022
  b3fd3a9a
- [SDAG] Remove single-result restriction on commutative CSE · 2570f226
  Itay Bookstein authored Jul 13, 2022
  2570f226
- [RISCV] Fold stack reload into sext.w by using lw instead of ld. · d7f2a633
  Craig Topper authored Jul 18, 2022
  d7f2a633
- Revert "[NVPTX] Use the mask() operator to initialize packed structs with pointers" · 1e451369
  Igor Kudrin authored Jul 18, 2022
  1e451369
- Revert "Inliner: don't mark call sites as 'nounwind' if that would be redundant" · 34437880
  Nicolai Hähnle authored Jul 18, 2022
  34437880
- Inliner: don't mark call sites as 'nounwind' if that would be redundant · 9905c379
  Nicolai Hähnle authored Jul 15, 2022
  9905c379
- [VP] IR expansion pass for VP gather and scatter · c00a44fa
  Lorenzo Albano authored Jul 18, 2022
  c00a44fa
- [AIX] support read global symbol of big archive · a6316d6d
  zhijian authored Jul 18, 2022
  a6316d6d
- [llvm-ar][test] Add testing for bitcode file handling · e97a6f61
  gbreynoo authored Jul 14, 2022
  e97a6f61
- [AMDGPU][MC][GFX11] AsmParser for op_sel for VOP3 dpp opcodes · c287bc48
  Petar Avramovic authored Jul 18, 2022
  c287bc48
- [LoopVectorize][NFC] Split reductions out from sve-tail-folding into new file · 34f81cfa
  David Sherwood authored Jul 14, 2022
  34f81cfa
- [AArch64][NFC] Simplify loop vectoriser tail-folding tests · 1e77b0c8
  David Sherwood authored Jul 15, 2022
  1e77b0c8
- [X86][FP16] Don't crash when lowering SELECT on fp16 vectors · 9234a7c0
  Benjamin Kramer authored Jul 18, 2022
  9234a7c0
- [CloneFunction][DebugInfo] Avoid cloning DILexicalBlocks of inlined subprograms · 44736c1d
  Kristina Bessonova authored Jul 18, 2022
  44736c1d
- [NVPTX] Use the mask() operator to initialize packed structs with pointers · 04e978cc
  Igor Kudrin authored Jul 18, 2022
  04e978cc
- [LAA] Add recursive IR walker for forked pointers · db8fcb2c
  Graham Hunter authored Jun 16, 2022
  db8fcb2c
- [AMDGPU][CodeGen] Support (register + immediate) SMRD offsets. · 432cbd78
  Ivan Kosarev authored Jul 18, 2022
  432cbd78
- [BasicBlockUtils] Don't drop callbr with unique successor · 8201e3ef
  Nikita Popov authored Jul 18, 2022
  8201e3ef
- [AMDGPU][CodeGen] Match SMRDs with constant bases and register offsets. · 9c66c02e
  Ivan Kosarev authored Jul 18, 2022
  9c66c02e
- [SimpleLoopUnswitch] Regenerate test checks (NFC) · 46d56157
  Nikita Popov authored Jul 18, 2022
  
  46d56157
- [Verifier] Make Verifier recognize undef tokens as correct IR · d693fd29
  Max Kazantsev authored Jul 18, 2022
  d693fd29
- [PowerPC] Add an ISEL pattern for i32 MULLI. · 28b1ba1c
  esmeyi authored Jul 18, 2022
  28b1ba1c
- [LoopUnroll] Regenerate test checks (NFC) · 118d8fe4
  Nikita Popov authored Jul 18, 2022
  
  118d8fe4
- [LV] Use PHI recipe instead of PredRecipe for subsequent uses. · 105032f5
  Florian Hahn authored Jul 18, 2022
  105032f5
- [IR] Don't treat callbr as indirect terminator · 11079e88
  Nikita Popov authored Jul 15, 2022
  11079e88
- [flang][openacc] Use TableGen to generate the clause parser · 048aaab1
  Valentin Clement authored Jul 18, 2022
  048aaab1