Commits · d60951f469919476dfae4ca3f5ccb153c7072f47 · Roger Ferrer / llvm-epi · GitLab

Dec 19, 2017
- [AMDGPU] Turn off MergeConsecutiveStores() before Instruction Selection for... · e4f067eb
  Mark Searles authored Dec 19, 2017
  e4f067eb
Dec 18, 2017
- [Memcpy Loop Lowering] Remove the fixed int8 lowering. · 5fb624a3
  Sean Fertile authored Dec 18, 2017
  5fb624a3
Dec 15, 2017
- Recommit CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.value · c41e2f6e
  Yaxun Liu authored Dec 15, 2017
  c41e2f6e
Dec 14, 2017
- Revert CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.value · f902ef0a
  Yaxun Liu authored Dec 14, 2017
  f902ef0a
Dec 13, 2017
- CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.value · a5315a04
  Yaxun Liu authored Dec 13, 2017
  a5315a04
Dec 12, 2017
- [MachineOperand][MIR] Add isRenamable to MachineOperand. · 60c43102
  Geoff Berry authored Dec 12, 2017
  60c43102
Dec 11, 2017
- LSR: Check more intrinsic pointer operands · 3e268cc0
  Matt Arsenault authored Dec 11, 2017
  3e268cc0
Dec 08, 2017
- AMDGPU/GCN: Bring processors in sync with AMDGPUUsage · c40d9f2e
  Konstantin Zhuravlyov authored Dec 08, 2017
  c40d9f2e
- AMDGPU: image_getlod and image_getresinfo do not read memory · 856777d8
  Matt Arsenault authored Dec 08, 2017
  856777d8
- AMDGPU: Report Arg's Value name in metadata if kernel_arg_name metadata is not available · e30f88f3
  Konstantin Zhuravlyov authored Dec 08, 2017
  e30f88f3
Dec 07, 2017
- [AMDGPU] Revert "[AMDGPU] Add options for waitcnt pass debugging; add instr count in debug output." · 9ebdbb43
  Mark Searles authored Dec 07, 2017
  9ebdbb43
- [AMDGPU] Add options for waitcnt pass debugging; add instr count in debug output. · a84d2348
  Mark Searles authored Dec 07, 2017
  a84d2348
- [AMDGPU] Add GCNHazardRecognizer::checkInlineAsmHazards() and... · d29f24ac
  Mark Searles authored Dec 07, 2017
  d29f24ac
- [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register. · a8a83d15
  Francis Visoiu Mistrih authored Dec 07, 2017
  a8a83d15
Dec 06, 2017
- AMDGPU Tests: Change a case to be run with -O0 · ffaed720
  Zvi Rackover authored Dec 06, 2017
  ffaed720
Dec 05, 2017
- AMDGPU: Fix SDWA crash on inline asm · 8ae38bc0
  Matt Arsenault authored Dec 05, 2017
  8ae38bc0
- AMDGPU: Fix infinite loop with dbg_value · 7f0a5273
  Matt Arsenault authored Dec 05, 2017
  7f0a5273
- AMDGPU: Fix crash when scheduling DBG_VALUE · 9a60c3ea
  Matt Arsenault authored Dec 05, 2017
  9a60c3ea
- AMDGPU/EG: Add a new FeatureFMA and use it to selectively enable FMA instruction · 39aeab4f
  Jan Vesely authored Dec 04, 2017
  39aeab4f
Dec 04, 2017
- AMDGPU: Disable fp64 support on pre GCN asics · d1c9b61e
  Jan Vesely authored Dec 04, 2017
  d1c9b61e
- AMDGPU: Fix creating invalid copy when adjusting dmask · 68f05052
  Matt Arsenault authored Dec 04, 2017
  68f05052
- [CodeGen] Unify MBB reference format in both MIR and debug output · 25528d6d
  Francis Visoiu Mistrih authored Dec 04, 2017
  25528d6d
- [AMDGPU] SDWA: add support for PRESERVE into SDWA peephole. · 5f7f32c3
  Sam Kolton authored Dec 04, 2017
  5f7f32c3
Dec 03, 2017
- CodeGen: Fix SelectionDAGISel::LowerArguments for sret addr space · 30e4608c
  Yaxun Liu authored Dec 03, 2017
  30e4608c
Dec 02, 2017
- CodeGen: Fix pointer info in SplitVecOp_EXTRACT_VECTOR_ELT/SplitVecRes_INSERT_VECTOR_ELT · 49477040
  Yaxun Liu authored Dec 02, 2017
  49477040
Dec 01, 2017
- [AMDGPU] SiFixSGPRCopies should not modify non-divergent PHI · c1425c9d
  Alexander Timofeev authored Dec 01, 2017
  c1425c9d
- AMDGPU: Use carry-less adds in FI elimination · 686d5c72
  Matt Arsenault authored Nov 30, 2017
  686d5c72
Nov 30, 2017
- AMDGPU: Use gfx9 carry-less add/sub instructions · 84445dd1
  Matt Arsenault authored Nov 30, 2017
  84445dd1
- [CodeGen] Always use `printReg` to print registers in both MIR and debug · c71cced0
  Francis Visoiu Mistrih authored Nov 30, 2017
  c71cced0
- [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output · 93ef1458
  Francis Visoiu Mistrih authored Nov 30, 2017
  93ef1458
- AMDGPU: Allow negative MUBUF vaddr for gfx9 · caf0ed4d
  Matt Arsenault authored Nov 30, 2017
  caf0ed4d
Nov 29, 2017
- AMDGPU: Use stricter regexes for add instructions · 9a7e29ae
  Matt Arsenault authored Nov 29, 2017
  9a7e29ae
- AMDGPU: Select DS insts without m0 initialization · 3f71c0e3
  Matt Arsenault authored Nov 29, 2017
  3f71c0e3
- AMDGPU: Enable IPRA · 607a7566
  Matt Arsenault authored Nov 28, 2017
  607a7566
Nov 28, 2017
- AMDGPU: Add num spilled s/vgprs to metadata · 06ae4ec7
  Konstantin Zhuravlyov authored Nov 28, 2017
  06ae4ec7
- [CodeGen] Print register names in lowercase in both MIR and debug output · 9d7bb0cb
  Francis Visoiu Mistrih authored Nov 28, 2017
  9d7bb0cb
- DAG: Legalize truncstores to illegal int types · e123aba9
  Matt Arsenault authored Nov 28, 2017
  e123aba9
Nov 27, 2017
- [AMDGPU] Update test nullptr.ll to use amdgiz environment · dcb6067d
  Yaxun Liu authored Nov 27, 2017
  dcb6067d
- [DAG] Do MergeConsecutiveStores again before Instruction Selection · db77e57e
  Nirav Dave authored Nov 27, 2017
  db77e57e
- [AMDGPU] Add custom lowering for llvm.log{,10}.{f16,f32} intrinsics · ad21f268
  Vedran Miletic authored Nov 27, 2017
  ad21f268