Commits · d60951f469919476dfae4ca3f5ccb153c7072f47 · Roger Ferrer / llvm-epi · GitLab

Dec 20, 2017
- Improve the test for r320216. NFC. · c07d4958
  Warren Ristow authored Dec 20, 2017
  c07d4958
- [X86] Implement the fusing of MUL+SUBADD to FMSUBADD · bc92e00f
  Craig Topper authored Dec 20, 2017
  bc92e00f
- [Hexagon] Adjust the value type for BCvt in LowerFormalArguments · 8f6b0c85
  Krzysztof Parzyszek authored Dec 20, 2017
  8f6b0c85
- [X86][AVX2] Split more shuffle tests into 'slow' and 'fast' variable shuffles · a50eec02
  Simon Pilgrim authored Dec 20, 2017
  a50eec02
- [ARM GlobalISel] Fix assertion in RegBankSelect · 75ce852a
  Diana Picus authored Dec 20, 2017
  75ce852a
- [ARM] Lower unsigned saturation to USAT · c3aa6d83
  Florian Hahn authored Dec 20, 2017
  c3aa6d83
- AArch64: fix one more place movi.2d could be created. · 6db5d027
  Tim Northover authored Dec 20, 2017
  6db5d027
- [X86] Optimize sign extends on index operand to gather/scatter to not sign extend past i32. · abed821c
  Craig Topper authored Dec 20, 2017
  abed821c
- [AArch64] Implement stack probing for windows · 2778fd0b
  Martin Storsjö authored Dec 20, 2017
  2778fd0b
- [PowerPC] fix a bug in redundant compare elimination · 11e571e0
  Hiroshi Inoue authored Dec 20, 2017
  11e571e0
- [X86] Improve coverage of fma negations. · b1ae03fd
  Craig Topper authored Dec 20, 2017
  b1ae03fd
- [X86] Fix probable typo in fma fneg test. · 171fb157
  Craig Topper authored Dec 20, 2017
  171fb157
Dec 19, 2017
- [CodeGen] Move printing MO_FPImmediate operands to MachineOperand::print · 3b265c8f
  Francis Visoiu Mistrih authored Dec 19, 2017
  3b265c8f
- [AMDGPU] Turn off MergeConsecutiveStores() before Instruction Selection for... · e4f067eb
  Mark Searles authored Dec 19, 2017
  e4f067eb
- [X86] Regenerate popcnt tests · 7cabb4c3
  Simon Pilgrim authored Dec 19, 2017
  7cabb4c3
- [GlobalISel][Legalizer] Fix crash when trying to lower G_FNEG of fp128 types. · b6ddbef6
  Amara Emerson authored Dec 19, 2017
  b6ddbef6
- [DAG] Elide overlapping store · 51425fa5
  Nirav Dave authored Dec 19, 2017
  51425fa5
- [X86][AVX512] Attempt target shuffle combining to different types instead of early-out · d873b6f6
  Simon Pilgrim authored Dec 19, 2017
  d873b6f6
- [X86][SSE] Add cpu feature for aggressive combining to variable shuffles · fd5df639
  Simon Pilgrim authored Dec 19, 2017
  fd5df639
- [ARM] Register the Thumb2SizeReducePass. NFC · 110844d2
  David Green authored Dec 19, 2017
  110844d2
- [X86][SSE] Use (V)PHMINPOSUW for vXi8 SMAX/SMIN/UMAX/UMIN horizontal reductions (PR32841) · f6d4ab6d
  Simon Pilgrim authored Dec 19, 2017
  f6d4ab6d
- [mips] Handle the emission of microMIPSr6 sll instruction when used as a nop. · 1ade566c
  Simon Dardis authored Dec 19, 2017
  1ade566c
- [X86] Don't extend v16i8 non-uniform shifts to v16i32 if we have BWI. Use v16i16 instead. · 13142b10
  Craig Topper authored Dec 19, 2017
  13142b10
- update_mir_test_checks: Accept IR as input as well as MIR · 4314f3ad
  Justin Bogner authored Dec 19, 2017
  4314f3ad
- TargetLoweringBase: Followup to r321035 · e29c0b88
  Matthias Braun authored Dec 19, 2017
  e29c0b88
- [Hexagon] Cache loads to select to avoid traversing mutating DAG · e704583f
  Krzysztof Parzyszek authored Dec 18, 2017
  e704583f
Dec 18, 2017
- [AArch64] Expand test coverage of vector element shuffling to Exynos · 687df638
  Evandro Menezes authored Dec 18, 2017
  687df638
- Fix more inconsistent line endings. NFC. · e4f5d010
  Dimitry Andric authored Dec 18, 2017
  e4f5d010
- [MachineOutliner] Recommit r320229 · 02c124d6
  Jessica Paquette authored Dec 18, 2017
  02c124d6
- [PPC] Also disable the pre-emit version of reg+reg to reg+imm transformation. · efc7c88e
  Benjamin Kramer authored Dec 18, 2017
  efc7c88e
- [Hexagon] Generate HVX code for vector sign-, zero- and any-extends · 6b589e59
  Krzysztof Parzyszek authored Dec 18, 2017
  6b589e59
- [X86] Regenerate test to improve codegen testing for D41350 · f947137e
  Simon Pilgrim authored Dec 18, 2017
  f947137e
- [YAML] Add support for non-printable characters · b213b27e
  Francis Visoiu Mistrih authored Dec 18, 2017
  b213b27e
- Reland "[mips] Fix the target specific instruction verifier" · fd8c65e8
  Simon Dardis authored Dec 18, 2017
  fd8c65e8
- [Memcpy Loop Lowering] Remove the fixed int8 lowering. · 5fb624a3
  Sean Fertile authored Dec 18, 2017
  5fb624a3
- Revert "[mips] Fix the target specific instruction verifier" · f70af977
  Simon Dardis authored Dec 18, 2017
  f70af977
- [mips] Fix the target specific instruction verifier · c3c0d459
  Simon Dardis authored Dec 18, 2017
  c3c0d459
- AArch64: work around how Cyclone handles "movi.2d vD, #0". · 9097a07e
  Tim Northover authored Dec 18, 2017
  9097a07e
- [ARM] Adjust test checks · fd967f2f
  Sam Parker authored Dec 18, 2017
  fd967f2f
- [DAGCombine] Move AND nodes to multiple load leaves · 00804efd
  Sam Parker authored Dec 18, 2017
  00804efd