Commits · d6218cc385920a462a99d28e0959c7300b25468a · Roger Ferrer / llvm-epi · GitLab

Sep 28, 2017
- [ARM] Restore the right frame pointer register in Int_eh_sjlj_longjmp · d6218cc3
  Martin Storsjö authored Sep 28, 2017
  d6218cc3
- [ARM] Fix SJLJ exception handling when manually chosen on a platform where it isn't default · adceba59
  Martin Storsjö authored Sep 28, 2017
  adceba59
- [X86] Use target independent ZERO_EXTEND/SIGN_EXTEND nodes were possible in LowerMULH · 3819be6c
  Craig Topper authored Sep 28, 2017
  3819be6c
- [X86] Move a setOperation action for ISD::TRUNCATE near another one in the... · fc104bfb
  Craig Topper authored Sep 28, 2017
  fc104bfb
- [X86] Use BWI instructions to improve lowering of v32i8 MULHU/S · ceff6da6
  Craig Topper authored Sep 28, 2017
  ceff6da6
- [X86] Remove dead code from X86ISelDAGToDAG.cpp multiply handling · fd6b8a67
  Craig Topper authored Sep 28, 2017
  fd6b8a67
- [X86] Use correct subvector index when combining two insert subvectors featuring zero vectors. · 71a8cf9f
  Craig Topper authored Sep 28, 2017
  71a8cf9f
- [SystemZ] Custom-expand ATOMIC_CMP_AND_SWAP_WITH_SUCCESS · 0f1de049
  Ulrich Weigand authored Sep 28, 2017
  0f1de049
- Use SDValue::getConstantOperandVal helper. NFCI. · 2ff33930
  Simon Pilgrim authored Sep 28, 2017
  2ff33930
- [mips] Remove codegen support for branch likely instructions. · c8e33c5c
  Simon Dardis authored Sep 28, 2017
  c8e33c5c
- [x86][AsmParser] Allow some more MS size directives · 566348f2
  Coby Tayree authored Sep 28, 2017
  566348f2
- Teach TargetInstrInfo::getInlineAsmLength to parse .space directives with integer arguments · 5518cbfc
  Alex Bradbury authored Sep 28, 2017
  5518cbfc
- [PowerPC] eliminate partially redundant compare instruction · 79c0bec0
  Hiroshi Inoue authored Sep 28, 2017
  79c0bec0
- [RISCV] Add common fixups and relocations · 9d3f1250
  Alex Bradbury authored Sep 28, 2017
  9d3f1250
- bpf: add new insns for bswap_to_le and negation · e9165f87
  Yonghong Song authored Sep 28, 2017
  e9165f87
- Reverted r313993. · 1c6f0bb6
  Galina Kistanova authored Sep 27, 2017
  1c6f0bb6
Sep 27, 2017
- [MachineOutliner] AArch64: Avoid saving + restoring LR if possible · 4cf187b5
  Jessica Paquette authored Sep 27, 2017
  4cf187b5
- Revert r314249 "Recommit r314151 "[X86] Make all the NOREX CodeGenOnly... · c16a4729
  Craig Topper authored Sep 27, 2017
  c16a4729
- Revert r314248 "[X86] Don't emit X86::MOV8rr_NOREX from X86InstrInfo::copyPhysReg." · e0d82900
  Craig Topper authored Sep 27, 2017
  e0d82900
- [X86][SSE] Pull out variable shuffle mask combine logic. NFCI. · 870007b4
  Simon Pilgrim authored Sep 27, 2017
  870007b4
- [X86] Rewrite the zero vector checks in lowerV2X128VectorShuffle to use the Zeroable APInt · 7b1d503d
  Craig Topper authored Sep 27, 2017
  7b1d503d
- [X86] In combineLoopSADPattern, pad result with zeros and use full size add... · 05f71dd0
  Craig Topper authored Sep 27, 2017
  05f71dd0
- [AArch64][Falkor] Ignore SP based loads in HW prefetch fixups. · c032b2be
  Geoff Berry authored Sep 27, 2017
  c032b2be
- [SimplifyCFG] add a struct to house optional folds (PR34603) · 0f9b4773
  Sanjay Patel authored Sep 27, 2017
  0f9b4773
- [PowerPC] eliminate unconditional branch to the next instruction · ed1ffa49
  Hiroshi Inoue authored Sep 27, 2017
  ed1ffa49
- [X86][AsmParser] fix PR32035 · 836c50cc
  Coby Tayree authored Sep 27, 2017
  836c50cc
- [X86][AVX] Improve (i4 bitcast (v4i1 x)) handling for 256-bit vector compare results. · 3b0d9e78
  Simon Pilgrim authored Sep 27, 2017
  3b0d9e78
- [ARM] isTruncateFree fix · 211f47aa
  Sam Parker authored Sep 27, 2017
  211f47aa
- [X86] Fix SJLJ struct offsets for x86_64 · aa1533bf
  Martin Storsjö authored Sep 27, 2017
  aa1533bf
- [X86] Remove erroneous callsite offsetting in SJLJ landing pads · eccaf04e
  Martin Storsjö authored Sep 27, 2017
  eccaf04e
- [X86] Use extract128BitVector in LowerMULH so we can extract from constant build vectors. · 177a3923
  Craig Topper authored Sep 27, 2017
  177a3923
Sep 26, 2017
- [AArch64][Falkor] Fix bug in falkor prefetcher fix pass. · bbfa246a
  Geoff Berry authored Sep 26, 2017
  bbfa246a
- [AArch64][Falkor] Fix correctness bug in falkor prefetcher fix pass and... · a4b2f5df
  Geoff Berry authored Sep 26, 2017
  a4b2f5df
- [X86] Fix register class name in a comment. NFC · b7e4c94c
  Craig Topper authored Sep 26, 2017
  b7e4c94c
- Recommit r314151 "[X86] Make all the NOREX CodeGenOnly instructions into... · 7f0eeb42
  Craig Topper authored Sep 26, 2017
  7f0eeb42
- [X86] Don't emit X86::MOV8rr_NOREX from X86InstrInfo::copyPhysReg. · ab3c0075
  Craig Topper authored Sep 26, 2017
  ab3c0075
- [X86] Fix typo in comment. NFC · 0768bced
  Craig Topper authored Sep 26, 2017
  0768bced
- [PowerPC] Reverting sequence of patches for elimination of comparison instructions · e22ebeab
  Nemanja Ivanovic authored Sep 26, 2017
  e22ebeab
- [X86][LLVM]Expanding Supports lowerInterleavedStore() in X86InterleavedAccess... · 645f777e
  Michael Zuckerman authored Sep 26, 2017
  645f777e
- [NVPTX] added match.{any,all}.sync instructions, intrinsics & builtins. · bab95c70
  Artem Belevich authored Sep 26, 2017
  bab95c70