Commits · d68bbdcc12dbdf81cdd3636e01f04b474e228980 · Roger Ferrer / llvm-epi · GitLab

Mar 29, 2016
- Add support for no-jump-tables · 2aab7f43
  Nirav Dave authored Mar 29, 2016
  2aab7f43
- Swift Calling Convention: add swiftself attribute. · f46262e0
  Manman Ren authored Mar 29, 2016
  f46262e0
- [x86] add tests to show current memset codegen · 7c615079
  Sanjay Patel authored Mar 29, 2016
  7c615079
- regenerate checks · 32de9628
  Sanjay Patel authored Mar 29, 2016
  32de9628
- fix CHECK_NOT -> CHECK-NOT · 32ddc544
  Junmo Park authored Mar 29, 2016
  32ddc544
- AVX-512: fixed a bug in fp_to_uint pattern on KNL · 95629caa
  Elena Demikhovsky authored Mar 29, 2016
  95629caa
- [PowerPC] Refactor popcnt[dw] target features · fa7057a4
  Hal Finkel authored Mar 29, 2016
  fa7057a4
- [Codegen] Decrease minimum jump table density. · 5e241b11
  Kyle Butt authored Mar 29, 2016
  5e241b11
- fix checks: *_DAG -> *-DAG · 1f867c6f
  Sanjay Patel authored Mar 28, 2016
  1f867c6f
- fix CHECK_NEXT -> CHECK-NEXT · 53f9ae28
  Sanjay Patel authored Mar 28, 2016
  53f9ae28
- fix CHECK_DAG -> CHECK-DAG · d9ebff8b
  Sanjay Patel authored Mar 28, 2016
  d9ebff8b
Mar 28, 2016
- fix CHECK_NEXT -> CHECK-NEXT · 52fe9d0e
  Sanjay Patel authored Mar 28, 2016
  52fe9d0e
- fix CHECK_LABEL -> CHECK-LABEL · 8f9e2696
  Sanjay Patel authored Mar 28, 2016
  8f9e2696
- trailing whitespace · a1e5ef62
  Sanjay Patel authored Mar 28, 2016
  a1e5ef62
- [X86][SSE] Vectorize a bit (AND/XOR/OR) op if a BUILD_VECTOR has the same op... · d3df400f
  Simon Pilgrim authored Mar 28, 2016
  d3df400f
- fix CHECK_NEXT -> CHECK-NEXT · 7092de4c
  Sanjay Patel authored Mar 28, 2016
  7092de4c
- MIRParser: Add %subreg.xxx syntax for subregister index operands · b74eb41d
  Matthias Braun authored Mar 28, 2016
  b74eb41d
- CodeGen: Correct specification of PHI nodes · 2bd8eeb6
  Matthias Braun authored Mar 28, 2016
  2bd8eeb6
- [AArch64] Do not lower scalar sdiv/udiv to a shifts + mul sequence when optimizing for minsize · 6a6bc750
  Haicheng Wu authored Mar 28, 2016
  6a6bc750
- [PowerPC] On the A2, popcnt[dw] are very slow · 7059d416
  Hal Finkel authored Mar 28, 2016
  7059d416
- Introduce MachineFunctionProperties and the AllVRegsAllocated property · ad154c83
  Derek Schuff authored Mar 28, 2016
  ad154c83
- AMDGPU/SI: Limit load clustering to 16 bytes instead of 4 instructions · a76bcc2e
  Tom Stellard authored Mar 28, 2016
  a76bcc2e
- [Hexagon] Improve handling of unaligned vector loads and stores · 2d65ea74
  Krzysztof Parzyszek authored Mar 28, 2016
  2d65ea74
- [Hexagon] Only use restore functions for single register at -Oz · bb63f666
  Krzysztof Parzyszek authored Mar 28, 2016
  bb63f666
- [lanai] Add Lanai backend. · fcef3e46
  Jacques Pienaar authored Mar 28, 2016
  fcef3e46
- AVX-512: Fixed ICMP instruction selection for i1 operands · 83f0647d
  Elena Demikhovsky authored Mar 28, 2016
  83f0647d
Mar 27, 2016
- [PowerPC] Map max/minnum intrinsics and fmax/fmin to ISD nodes for CTR-based loop legality · 0b37175c
  Hal Finkel authored Mar 27, 2016
  0b37175c
Mar 26, 2016
- [X86][AVX] Enabled SMUL_LOHI/UMUL_LOHI v8i32 vectors on AVX1 targets · dcdf8503
  Simon Pilgrim authored Mar 26, 2016
  dcdf8503
- [X86][AVX] Enabled MULHS/MULHU v16i16 vectors on AVX1 targets · e4dbeb40
  Simon Pilgrim authored Mar 26, 2016
  e4dbeb40
- [X86][SSE] Add MULHS/MULHU custom lowering for i8 vectors · 3eef33a8
  Simon Pilgrim authored Mar 26, 2016
  3eef33a8
- [X86][SSE] Added v64i8 vector integer multiply tests · 7b36cdae
  Simon Pilgrim authored Mar 26, 2016
  7b36cdae
- [X86][AVX512BW] AVX512BW can sign-extend v32i8 to v32i16 for simpler v32i8 multiplies. · 7379a706
  Simon Pilgrim authored Mar 26, 2016
  7379a706
- [PowerPC] Disable the CTR optimization in the presence of {min,max}num · b549ab02
  David Majnemer authored Mar 26, 2016
  b549ab02
- [X86][SSE] Refreshed vector integer multiply tests · 9a5f19f5
  Simon Pilgrim authored Mar 26, 2016
  9a5f19f5
Mar 25, 2016
- [X86] Emit a proper ADJCALLSTACKDOWN in EmitLoweredTLSAddr · 020e890a
  David Majnemer authored Mar 25, 2016
  020e890a
- [MachineCopyPropagation] Expose more dead copies across instructions with regmasks · 36c53fe1
  Jun Bum Lim authored Mar 25, 2016
  36c53fe1
- Prevent construction of cycle in DAG store merge · fa250cad
  Nirav Dave authored Mar 25, 2016
  fa250cad
- ARM: maintain BB ordering when expanding WIN__DBZCHK · 750a90df
  Saleem Abdulrasool authored Mar 25, 2016
  750a90df
- [X86] Use "and $0" and "orl $-1" to store 0 and -1 when optimizing for minsize · 5f916d3d
  Hans Wennborg authored Mar 25, 2016
  5f916d3d
- X86: Use push-pop for materializing 8-bit immediates for minsize (take 2) · 4ae5119e
  Hans Wennborg authored Mar 25, 2016
  4ae5119e