Commits · d7b0e5525a4e809cf61a4e1c82f000af781cbab4 · Roger Ferrer / llvm-epi · GitLab

Aug 04, 2021
- X86: fix frame offset calculation with mandatory tail calls · d7b0e552
  Tim Northover authored Aug 04, 2021
  d7b0e552
- Introduce intrinsic llvm.isnan · 16ff91eb
  Serge Pavlov authored Aug 04, 2021
  16ff91eb
- [AMDGPU] Ignore call graph node which does not have function info. · 596e61c3
  hsmahesha authored Aug 04, 2021
  596e61c3
- [WebAssembly] Misc. cosmetic changes in EH (NFC) · 9bd02c43
  Heejin Ahn authored Aug 01, 2021
  9bd02c43
- [MC][CodeGen] Emit constant pools earlier · ad253446
  Arthur Eubanks authored Aug 02, 2021
  ad253446
- [AArch64][GlobalISel] Widen G_SELECT before clamping it · 56437363
  Jessica Paquette authored Aug 03, 2021
  56437363
Aug 03, 2021
- [RISCV] Add scheduling resources for V · 63a5ac4e
  Evandro Menezes authored Jul 24, 2021
  63a5ac4e
- [AArch64] Prefer fmov over orr v.16b when copying f32/f64 · bd07c2e2
  David Green authored Aug 03, 2021
  bd07c2e2
- [RISCV] Indicate that RISCVMergeBaseOffsetOpt preserves the CFG. · deaeb16d
  Craig Topper authored Aug 02, 2021
  deaeb16d
- [X86] Add title comment to separate the "CPU Families" features from the other... · d3917bbf
  Simon Pilgrim authored Aug 03, 2021
  d3917bbf
- [RISCV] Support simple fractional steps in matching VID sequences · cba6aab9
  Fraser Cormack authored Jul 16, 2021
  cba6aab9
- [AArch64InstPrinter] Change printAddSubImm to comment imm value when shifted · 0d8cd4e2
  Jason Molenda authored Aug 03, 2021
  0d8cd4e2
- [AArch64][AsmParser] NFC: Use helpers in matrix tile list parsing · a02bbeea
  Cullen Rhodes authored Aug 03, 2021
  
  a02bbeea
- [AMDGPU] Legalize operands of V_ADDC_U32_e32 and friends · 40202b13
  Jay Foad authored Jul 27, 2021
  40202b13
- Reland: "[WebAssembly] Add new pass to lower int/ptr conversions of reftypes" · d3a0a65b
  Paulo Matos authored Jul 28, 2021
  d3a0a65b
- [RISCV] Teach VSETVLI insertion to merge the unused VSETVLI with the one need... · 7900ee0b
  Jianjian GUAN authored Aug 03, 2021
  7900ee0b
Aug 02, 2021
- [BasicTTIImpl][LoopUnroll] getUnrollingPreferences(): emit ORE remark when... · 6f6e9a86
  Roman Lebedev authored Aug 03, 2021
  6f6e9a86
- [AArch64][GlobalISel] Emit extloads for ZExt/SExt values in assignValueToAddress · bd13c8e6
  Jessica Paquette authored Aug 02, 2021
  bd13c8e6
- Revert "[WebAssembly] Add new pass to lower int/ptr conversions of reftypes" · 245f2ee6
  Paulo Matos authored Aug 02, 2021
  245f2ee6
- [WebAssembly] Add new pass to lower int/ptr conversions of reftypes · ce1c59de
  Paulo Matos authored Jul 28, 2021
  ce1c59de
- [WebAssembly] Compute known bits for SIMD bitmask intrinsics · 417e5006
  Thomas Lively authored Aug 02, 2021
  417e5006
- [ARM] Remove setPreservesCFG from ARMBlockPlacement · c423a586
  David Green authored Aug 02, 2021
  c423a586
- [AArch64] Optimise min/max lowering in ISel · b01417d3
  Irina Dobrescu authored Jul 22, 2021
  b01417d3
- [AMDGPU] Disable NSA for BVH instructions when appropriate · 675c9423
  Carl Ritson authored Aug 02, 2021
  675c9423
- [TTI] Add basic SK_InsertSubvector shuffle mask recognition · 7397dcb4
  Simon Pilgrim authored Aug 02, 2021
  7397dcb4
- Fix MSVC signed/unsigned comparison warning. NFCI. · 05790501
  Simon Pilgrim authored Jul 31, 2021
  
  05790501
- [ARM] Revert WLSTP to DLSTP if the target block is out of range · 28293918
  David Green authored Aug 02, 2021
  28293918
- [AArch64][AsmParser] NFC: Parser.Lex() -> Lex() · 7ed0120d
  Cullen Rhodes authored Aug 02, 2021
  7ed0120d
- [AMDGPU][GlobalISel] Add missing default mapping for BVH intrinsics · a441de6d
  Carl Ritson authored Aug 02, 2021
  a441de6d
Jul 31, 2021
- [RISCV] Rename vector inline constraint from 'v' to 'vr' and 'vm' in IR. · 8b33839f
  Hsiangkai Wang authored Jul 30, 2021
  8b33839f
- Fix the default alignment of i1 vectors. · bdd55b2f
  Eli Friedman authored Jul 31, 2021
  bdd55b2f
- [RISCV] Rename RISCVISD::FCVT_W_RV64 to FCVT_W_RTZ_RV64. NFC · 593059b3
  Craig Topper authored Jul 31, 2021
  593059b3
- [ARM] Switch order of creating VADDV and VMLAV. · 15a1d7e8
  David Green authored Jul 31, 2021
  15a1d7e8
- GlobalISel: Scalarize unaligned vector stores · ebc17a0d
  Matt Arsenault authored Jul 27, 2021
  ebc17a0d
- [AArch64] Legalize MVT::i64x8 in DAG isel lowering · 7d940432
  Alexandros Lamprineas authored Jul 31, 2021
  7d940432
Jul 30, 2021
- [ARM] Distribute reductions based on ascending load offset · 69cdaddd
  David Green authored Jul 30, 2021
  69cdaddd
- AMDGPU/GlobalISel: Remove special case lowering for non-pow-2 stores · faccf427
  Matt Arsenault authored Jun 06, 2021
  faccf427
- [ARM] Attempt to distribute reductions · 532d05b7
  David Green authored Jul 30, 2021
  532d05b7
- [ARM] Turn vecreduce_add(add(x, y)) into vecreduce(x) + vecreduce(y) · 4b563067
  David Green authored Jul 30, 2021
  4b563067
- [AArch64][SME] Introduce feature for streaming mode · 3a349d22
  Cullen Rhodes authored Jul 30, 2021
  3a349d22