Commits · d7de7ac370181ec0acb42fa2e4085c870868c4e0 · Roger Ferrer / llvm-epi · GitLab

Feb 11, 2020
- [X86] Raise the latency for VectorImul from 4 to 5 in Skylake scheduler models · d7de7ac3
  Craig Topper authored Feb 11, 2020
  d7de7ac3
- Restore "[WPD/LowerTypeTests] Delay lowering/removal of type tests until after ICP" · 80d0a137
  Teresa Johnson authored Feb 06, 2020
  80d0a137
- [BPF] implement isTruncateFree and isZExtFree in BPFTargetLowering · 29bc5dd1
  Yonghong Song authored Feb 05, 2020
  29bc5dd1
- [Attributor] Return uses do not free pointers · f9555392
  Johannes Doerfert authored Jan 10, 2020
  f9555392
- [Attributor][FIX] Remove duplicate, half-broken functionality · 4c62a358
  Johannes Doerfert authored Jan 12, 2020
  4c62a358
- [SystemZ] Fix new test case for expensive checks. · 509bac03
  Jonas Paulsson authored Feb 11, 2020
  509bac03
- [test][DebugInfo][NFC] Fix line endings · 47f7df89
  James Henderson authored Feb 11, 2020
  
  47f7df89
- [SystemZ] Bugfix in emitSelect() · 0311e28e
  Jonas Paulsson authored Feb 10, 2020
  0311e28e
- [SCCP] Remove forcedconstant, go to overdefined instead · aadb635e
  Florian Hahn authored Feb 11, 2020
  aadb635e
- [ARM][MVE] Tail-Predication: recognise (again) active lanes IR pattern · 6b0ed508
  Sjoerd Meijer authored Feb 11, 2020
  6b0ed508
- [RISCV] Optimize seteq/setne pattern expansions for better code size · db875f66
  Andrew Wei authored Feb 11, 2020
  db875f66
- Revert "[DSE] Add first version of MemorySSA-backed DSE (Bottom up walk)." · 42f8b915
  Kadir Cetinkaya authored Feb 11, 2020
  42f8b915
- [X86][SSE] lowerShuffleAsBitRotate - lower to vXi8 shuffles to ROTL on pre-SSSE3 targets · 11c16e71
  Simon Pilgrim authored Feb 11, 2020
  11c16e71
- [Mips] Add intrinsics for 4-byte and 8-byte MSA loads/stores. · 5ba931a8
  Mirko Brkusanin authored Feb 11, 2020
  5ba931a8
- [AArch64][SVE] Add SVE2 intrinsics for complex integer dot product · e7755f9e
  Kerry McLaughlin authored Feb 11, 2020
  e7755f9e
- [DebugInfo] Teach LDV how to handle identical variable fragments · 1e407993
  OCHyams authored Feb 11, 2020
  1e407993
- [llvm-readobj][test] - Add a test for --elf-cg-profile option. · 60e9b588
  Georgii Rymar authored Feb 06, 2020
  60e9b588
- [X86] Custom lower ISD::FP16_TO_FP and ISD::FP_TO_FP16 on f16c targets instead... · 798305d2
  Craig Topper authored Feb 09, 2020
  798305d2
- [llvm][TableGen] Define FieldInit::isConcrete overload · 52086f80
  River Riddle authored Feb 10, 2020
  52086f80
Feb 10, 2020
- [EarlyCSE] avoid crashing when detecting min/max/abs patterns (PR41083) · b8ebc11f
  Sanjay Patel authored Feb 10, 2020
  b8ebc11f
- Remove lit feature object-emission · 7683a084
  Ted Woodward authored Feb 10, 2020
  7683a084
- [AIX] Enable frame pointer for AIX and add related test suite · 660b0d7f
  Xiangling Liao authored Feb 10, 2020
  660b0d7f
- [Transforms] add phase ordering tests for min/max/abs; NFC · 0ad6e726
  Sanjay Patel authored Feb 10, 2020
  0ad6e726
- [InstCombine] fix use check when canonicalizing abs/nabs · 62ce7e65
  Sanjay Patel authored Feb 10, 2020
  62ce7e65
- [InstCombine] add tests for abs with extra use of operand; NFC · 93073e52
  Sanjay Patel authored Feb 10, 2020
  
  93073e52
- [AIX][XCOFF] Support Mergeable2ByteCString and Mergeable4ByteCString · aa86311e
  diggerlin authored Feb 10, 2020
  aa86311e
- [LoopCacheAnalysis]: Add support for negative stride · 1f554200
  Rachel Craik authored Feb 10, 2020
  1f554200
- [SystemZ] Add a subtarget cache like some other targets already have. · fcdb99e0
  Jonas Paulsson authored Feb 05, 2020
  fcdb99e0
- AMDGPU: Move R600 test compatability hack · 7af7b96a
  Matt Arsenault authored Feb 09, 2020
  7af7b96a
- [X86] combineConcatVectorOps - combine X86ISD::PACKSS ops · f3190748
  Simon Pilgrim authored Feb 10, 2020
  
  f3190748
- [X86] combineConcatVectorOps - combine X86ISD::VPERMI ops · 74c0f98c
  Simon Pilgrim authored Feb 10, 2020
  
  74c0f98c
- [X86] combineConcatVectorOps - combine VSHLI/VSRAI/VSRLI ops · 2463b8c9
  Simon Pilgrim authored Feb 10, 2020
  2463b8c9
- Revert "[InstCombine][DebugInfo] Fold constants wrapped in metadata" · 98294452
  David Stenberg authored Feb 10, 2020
  98294452
- [X86] Add lowerShuffleAsBitRotate (PR44379) · 06617c45
  Simon Pilgrim authored Feb 10, 2020
  06617c45
- [DSE,MSSA] Adjust mda-with-dbg-values.ll to MSSA backed DSE. · 74f03e4f
  Florian Hahn authored Feb 10, 2020
  74f03e4f
- [AArch64] Make Read Write System Registers Read Only · a67db836
  Luke Geeson authored Feb 10, 2020
  a67db836
- [SelectionDAG] Optimize build_vector of truncates and shifts · 7cddd15e
  Sebastian Neubauer authored Jan 31, 2020
  7cddd15e
- [DebugInfo][test] Replace pre-canned binary test · 1dc62d03
  James Henderson authored Feb 07, 2020
  1dc62d03
- [SystemZ] Add implementation for the intrinsic llvm.read_register · 34946dfd
  Kai Nacke authored Jan 08, 2020
  34946dfd
- [llvm-readobj] - Change the error to warning when a section name is unknown. · 0378afc4
  Georgii Rymar authored Feb 05, 2020
  0378afc4