Commits · d7e11ee3421f4dd478283379622d88a2ffc3da30 · Roger Ferrer / llvm-epi · GitLab

Jun 01, 2018
- [X86] Add fast-isel tests for avx512vbmi2 instructions. · d7e11ee3
  Craig Topper authored Jun 01, 2018
  d7e11ee3
- [Hexagon] Select HVX code for vector CTPOP, CTLZ, and CTTZ · aec2c0c9
  Krzysztof Parzyszek authored Jun 01, 2018
  aec2c0c9
- [SelectionDAG] Expand UADDO/USUBO into ADD/SUBCARRY if legal for target · 0b6187c1
  Krzysztof Parzyszek authored Jun 01, 2018
  0b6187c1
- [x86] NFC. Reautogenerate test/CodeGen/X86/vector-half-conversions.ll · b34afcec
  Alexander Ivchenko authored Jun 01, 2018
  b34afcec
- [Utils][X86] Help update_llc_test_checks.py to recognise retl/retq to reduce... · ee769444
  Simon Pilgrim authored Jun 01, 2018
  ee769444
- [AArch64][GlobalISel] Zero-extend s1 values when returning. · 5a3bb68e
  Amara Emerson authored Jun 01, 2018
  5a3bb68e
- [mips] Select the correct instruction for computing frameindexes · ee67dcb8
  Simon Dardis authored Jun 01, 2018
  ee67dcb8
- AMDGPU: Switch some half using-tests to use amdhsa · 72a9f52c
  Matt Arsenault authored Jun 01, 2018
  72a9f52c
- [WebAssembly] Update to the new names for the memory intrinsics. · 91ab25bb
  Dan Gohman authored May 31, 2018
  91ab25bb
- [WebAssembly] Fix the signatures for the __mulo* libcalls. · b17de645
  Dan Gohman authored May 31, 2018
  b17de645
- [WebAssembly] Support instruction selection for catching exceptions · 5ef4d5f9
  Heejin Ahn authored May 31, 2018
  5ef4d5f9
- [WebAssembly] Add Wasm exception handling prepare pass · 99d60e0d
  Heejin Ahn authored May 31, 2018
  99d60e0d
May 31, 2018
- [AMDGPU] Construct memory clauses before RA · 739174c4
  Stanislav Mekhanoshin authored May 31, 2018
  739174c4
- [AMDGPU] Fixed incorrect -mcpu=gfx800 in xnor.ll test. NFC. · 7137f609
  Stanislav Mekhanoshin authored May 31, 2018
  7137f609
- Relax GOTPCREL relocations for tail jmp instructions. · d10c4e07
  Sriraman Tallam authored May 31, 2018
  d10c4e07
- [X86][SSE] Recognise splat rotations and expand back to shift ops. · ff0623cd
  Simon Pilgrim authored May 31, 2018
  ff0623cd
- [X86] Introduce WriteFLDC for x87 constant loads. · 2e41c5a7
  Clement Courbet authored May 31, 2018
  2e41c5a7
- [X86] Extract latency of fldz/fld1 in separate classes. · b78ab509
  Clement Courbet authored May 31, 2018
  b78ab509
- [X86][SSE] Add support for detecting SUB(SPLAT_BV, SPLAT) cases for shift-rotate patterns. · 346886bc
  Simon Pilgrim authored May 31, 2018
  346886bc
- [AArch64] Reverted rL333427 fixing Clang UnitTest Failure · 2e09995d
  Luke Geeson authored May 31, 2018
  2e09995d
- AMDGPU/R600: Make sure functions are cacheline aligned · f5016b79
  Jan Vesely authored May 31, 2018
  f5016b79
- [GlobalISel][AArch64] LegalizerInfo verifier: Fixing bugs exposed by LegalizerInfo::verify(...) · 5a65eb75
  Roman Tereshin authored May 31, 2018
  5a65eb75
- [GlobalISel][AArch64] LegalizerInfo verifier: Adding... · 8f1753e9
  Roman Tereshin authored May 30, 2018
  8f1753e9
May 30, 2018
- [X86] Update the fast-isel tests for _mm_rcp_ss, _mm_rsqrt_ss, and _mm_sqrt_ss... · 2fbbffa4
  Craig Topper authored May 30, 2018
  2fbbffa4
- [X86][AVX512BW] Fixed check prefix copy+paste typo in avx512bw-intrinsics.ll · 3173f735
  Simon Pilgrim authored May 30, 2018
  3173f735
- AMDGPU: Use better alignment for kernarg lowering · 7b4826e6
  Matt Arsenault authored May 30, 2018
  7b4826e6
- [AMDGPU][Waitcnt] Fix handling of loops with many bottom blocks · 10545414
  Mark Searles authored May 30, 2018
  10545414
- [X86] Lowering FMA intrinsics to native IR (LLVM part) · 890e363e
  Gabor Buella authored May 30, 2018
  890e363e
- [X86][AVX512] Replace -cpu=knl with -mattr=+avx512f for avx512-intrinsics tests · 8df8b129
  Simon Pilgrim authored May 30, 2018
  8df8b129
- [X86][SSE] Remove unnecessary -cpu from sttni tests · 173e225f
  Simon Pilgrim authored May 30, 2018
  173e225f
- [X86][SSE] Replace -cpu with equivalent -mattr for vec_cast tests · 61b859dc
  Simon Pilgrim authored May 30, 2018
  61b859dc
- [Hexagon] Use vector align-left when shift amount fits in 3 bits · 89871746
  Krzysztof Parzyszek authored May 30, 2018
  89871746
- [Sparc] Select correct register class for FP register constraints · 60e6ce41
  Daniel Cederman authored May 30, 2018
  60e6ce41
May 29, 2018
- [X86] Rename the operands in the recently introduced MOVSS+FMA patterns so... · aba57bfe
  Craig Topper authored May 29, 2018
  aba57bfe
- [X86] Fix a potential crash that occur after r333419. · 5439b3d1
  Craig Topper authored May 29, 2018
  5439b3d1
- AMDGPU: Fix broken check lines · 4b3829d8
  Matt Arsenault authored May 29, 2018
  4b3829d8
- AMDGPU: Round up kernel argument allocation size · 1ea0402e
  Matt Arsenault authored May 29, 2018
  1ea0402e
- [RISCV] Add peepholes for Global Address lowering patterns · 97684419
  Sameer AbuAsal authored May 29, 2018
  97684419
- AMDGPU: Always set COMPUTE_PGM_RSRC2.ENABLE_TRAP_HANDLER to zero for AMDHSA as · 2ca6b1f2
  Konstantin Zhuravlyov authored May 29, 2018
  2ca6b1f2
- [ARM] Enable SETCCCARRY lowering for Thumb1. · 63fead0f
  Eli Friedman authored May 29, 2018
  63fead0f